- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4527 > AGL125V5-CSG196I (Microsemi SoC)IC FPGA 1KB FLASH 125K 196-CSP PDF資料下載
參數(shù)資料
| 型號(hào)： | AGL125V5-CSG196I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 229/250頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1KB FLASH 125K 196-CSP |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | IGLOO |
| 邏輯元件/單元數(shù)： | 3072 |
| RAM 位總計(jì)： | 36864 |
| 輸入/輸出數(shù)： | 133 |
| 門數(shù)： | 125000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 196-TFBGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 196-CSP（8x8） |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)當(dāng)前第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)
IGLOO Device Family Overview
1-2
Revision 23
Flash Advantages
Low Power
Flash-based IGLOO devices exhibit power characteristics similar to those of an ASIC, making them an
ideal choice for power-sensitive applications. IGLOO devices have only a very limited power-on current
surge and no high-current transition period, both of which occur on many FPGAs.
IGLOO devices also have low dynamic power consumption to further maximize power savings; power is
even further reduced by the use of a 1.2 V core voltage.
Low dynamic power consumption, combined with low static power consumption and Flash*Freeze
technology, gives the IGLOO device the lowest total system power offered by any FPGA.
Security
Nonvolatile, flash-based IGLOO devices do not require a boot PROM, so there is no vulnerable external
bitstream that can be easily copied. IGLOO devices incorporate FlashLock, which provides a unique
combination of reprogrammability and design security without external overhead, advantages that only
an FPGA with nonvolatile flash programming can offer.
IGLOO devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of
protection in the FPGA industry for intellectual property and configuration data. In addition, all FlashROM
data in IGLOO devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192)
bit block cipher encryption standard. AES was adopted by the National Institute of Standards and
Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO devices have a built-in AES
decryption engine and a flash-based AES key that make them the most comprehensive programmable
logic device security solution available today. IGLOO devices with AES-based security provide a high
level of protection for remote field updates over public networks such as the Internet, and are designed to
ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves.
Security, built into the FPGA fabric, is an inherent component of the IGLOO family. The flash cells are
located beneath seven metal layers, and many device design and layout techniques have been used to
make invasive attacks extremely difficult. The IGLOO family, with FlashLock and AES security, is unique
in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with
industry-standard security, making remote ISP possible. An IGLOO device provides the best available
security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO FPGAs do
not require system configuration components such as EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system
reliability.
Instant On
Flash-based IGLOO devices support Level 0 of the Instant On classification standard. This feature helps
in system component initialization, execution of critical tasks before the processor wakes up, setup and
configuration of memory blocks, clock generation, and bus activity management. The Instant On feature
of flash-based IGLOO devices greatly simplifies total system design and reduces total system cost, often
eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system
power will not corrupt the IGLOO device's flash configuration, and unlike SRAM-based FPGAs, the
device will not have to be reloaded when system power is restored. This enables the reduction or
complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock
generator devices from the PCB design. Flash-based IGLOO devices simplify total system design and
reduce cost and design risk while increasing system reliability and improving system initialization time.
IGLOO flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost
instantly (within 1 s) and the device retains configuration and data in registers and RAM. Unlike SRAM-
based FPGAs the device does not need to reload configuration and design state from external memory
components; instead it retains all necessary information to resume operation immediately.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL125V5-CS196I | IC FPGA 1KB FLASH 125K 196-CSP |
| A3P060-2FG144I | IC FPGA 1KB FLASH 60K 144-FBGA |
| ABM43DSEN-S13 | CONN EDGECARD EXTEND 86POS .156 |
| A3P060-2FGG144I | IC FPGA 1KB FLASH 60K 144-FBGA |
| EP4CE6E22C6N | IC CYCLONE IV FPGA 6K 144EQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL125V5-DIELOT | 制造商:Microsemi Corporation 功能描述:AGL125V5-DIELOT - Gel-pak, waffle pack, wafer, diced wafer on film |
| AGL125V5-FCS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL125V5-FCS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL125V5-FCS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL125V5-FCS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。