IGLOO Low Power Flash FPGAs
Revision 23
2-129
1.2 V DC Core Voltage
Table 2-196 FIFO
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
Description
Std.
Units
tENS
REN, WEN Setup Time
4.13
ns
tENH
REN, WEN Hold Time
0.31
ns
tBKS
BLK Setup Time
0.47
ns
tBKH
BLK Hold Time
0.00
ns
tDS
Input Data (WD) Setup Time
1.56
ns
tDH
Input Data (WD) Hold Time
0.49
ns
tCKQ1
Clock High to New Data Valid on RD (flow-through)
6.80
ns
tCKQ2
Clock High to New Data Valid on RD (pipelined)
3.62
ns
tRCKEF
RCLK High to Empty Flag Valid
7.23
ns
tWCKFF
WCLK High to Full Flag Valid
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
26.61
ns
tRSTFG
RESET Low to Empty/Full Flag Valid
7.12
ns
tRSTAF
RESET Low to Almost Empty/Full Flag Valid
26.33
ns
tRSTBQ
RESET Low to Data Out Low on RD (flow-through)
4.09
ns
RESET Low to Data Out Low on RD (pipelined)
4.09
ns
tREMRSTB
RESET Removal
1.23
ns
tRECRSTB
RESET Recovery
6.58
ns
tMPWRSTB
RESET Minimum Pulse Width
1.18
ns
tCYC
Clock Cycle Time
10.90
ns
FMAX
Maximum Frequency for FIFO
92
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.