Revision 13 5-3 Revision 9 (continued) The example in the paragraph above Table 2-31 Duration of Short Circuit Event" />
參數(shù)資料
型號： AGLE3000V2-FG896
廠商： Microsemi SoC
文件頁數(shù)： 67/166頁
文件大?。?/td> 0K
描述： IC FPGA 1KB FLASH 3M 896-FBGA
標(biāo)準(zhǔn)包裝： 27
系列： IGLOOe
邏輯元件/單元數(shù)： 75264
RAM 位總計： 516096
輸入/輸出數(shù)： 620
門數(shù)： 3000000
電源電壓： 1.14 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 896-BGA
供應(yīng)商設(shè)備封裝： 896-FBGA（31x31）
IGLOOe Low Power Flash FPGAs
Revision 13
5-3
Revision 9
(continued)
The example in the paragraph above Table 2-31 Duration of Short Circuit Event before
Failure was revised to change the maximum temperature from 110°C to 100°C, with an
example of six months instead of three months (SAR 32287).
The notes regarding drive strength in the "Summary of I/O Timing Characteristics –
LVCMOS Wide Range" section tables were revised for clarification. They now state that
the minimum drive strength for the default software configuration when run in wide range
is ±100 A. The drive strength displayed in software is supported in normal range only.
For a detailed I/V curve, refer to the IBIS models (SAR 34766).
The AC Loading figures in the "Single-Ended I/O Characteristics" section were updated
Settings" section (SAR 34886).
The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 34793): "It
uses a 5 V–tolerant input buffer and push-pull output buffer."
Specification were updated. A note was added to both tables indicating that when the
CCC/PLL core is generated by Microsemi core generator software, not all delay values
of the specified delay increments are available (SAR 34818).
The following figures were deleted. Reference was made to a new application note,
FPGAs, which covers these cases in detail (SAR 34869).
Figure 2-46 Write Access after Write onto Same Address
Figure 2-47 Read Access after Write onto Same Address
Figure 2-48 Write Access after Read onto Same Address
The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics"
tables, Figure 2-50 FIFO Reset, and the FIFO "Timing Characteristics" tables were
revised to ensure consistency with the software names (SAR 35749).
The "Pin Descriptions and Packaging" chapter is new (SAR 34768).
Package names used in the "Package Pin Assignments" section were revised to match
standards given in Package Mechanical Drawings (SAR 34768)
July 2010
The versioning system for datasheets has been changed. Datasheets are assigned a
revision number that increments each time the datasheet is revised. The "IGLOOe
Device Status" table on page II indicates the status for each device in the device family.
N/A
Revision
Changes
Page
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGLE3000V2-FG896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FG896I 功能描述:IC FPGA 1KB FLASH 3M 896-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOOe 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
AGLE3000V2-FG896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE3000V2-FGG484 功能描述:IC FPGA 1KB FLASH 3M 484-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOOe 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
AGLE3000V2-FGG484I 功能描述:IC FPGA 1KB FLASH 3M 484-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOOe 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75）
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