參數(shù)資料
型號(hào)： AGLE600V2-FFG256C
元件分類： FPGA
英文描述： FPGA, 13824 CLBS, 600000 GATES, PBGA256
封裝： 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-256
文件頁數(shù)： 120/156頁
文件大?。?/td> 5023K
代理商： AGLE600V2-FFG256C
IGLOOe DC and Switching Characteristics
2- 52
Advance v0.3
HSTL Class I
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
IGLOOe devices support Class I. This provides a differential amplifier input buffer and a push-pull
output buffer.
Table 2-81 Minimum and Maximum DC Input and Output Levels
HSTL Class I
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL IIH
Drive Strength Min., V Max., V
Min., V
Max., V Max., V
Min., V mA mA Max., mA1 Max., mA1 A2 A2
8 mA
–0.3
VREF – 0.1 VREF + 0.1
3.6
0.4
VCCI – 0.4 8
8
32
39
10 10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-17 AC Loading
Table 2-82 AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point*
(V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF – 0.1
VREF + 0.1
0.750.750.75
20
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Test Point
20 pF
50
HSTL
Class I
VTT
相關(guān)PDF資料
PDF描述
AGLE600V2-FFG484C FPGA, 13824 CLBS, 600000 GATES, PBGA484
AGLE600V2-FFGG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V2-FFGG484C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V2-FG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
AGLE600V2-FGG256C FPGA, 13824 CLBS, 600000 GATES, PBGA256
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