Revision 13 2-11 Power Consumption of Various Internal Resources Table 2-15 Different Components Contributing" />
參數(shù)資料
型號： AGLE600V2-FG256I
廠商： Microsemi SoC
文件頁數(shù)： 85/166頁
文件大小： 0K
描述： IC FPGA 1KB FLASH 600K 256-FBGA
標準包裝： 90
系列： IGLOOe
邏輯元件/單元數(shù)： 13824
RAM 位總計： 110592
輸入/輸出數(shù)： 165
門數(shù)： 600000
電源電壓： 1.14 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FPBGA（17x17）
IGLOOe Low Power Flash FPGAs
Revision 13
2-11
Power Consumption of Various Internal Resources
Table 2-15 Different Components Contributing to the Dynamic Power Consumption in IGLOOe Devices
For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Parameter
Definition
Device-Specific Dynamic
Contributions (W/MHz)
AGLE600
AGLE3000
PAC1
Clock contribution of a Global Rib
19.7
12.77
PAC2
Clock contribution of a Global Spine
4.16
1.85
PAC3
Clock contribution of a VersaTile row
0.88
PAC4
Clock contribution of a VersaTile used as a sequential module
0.11
PAC5
First contribution of a VersaTile used as a sequential module
0.057
PAC6
Second contribution of a VersaTile used as a sequential module
0.207
PAC7
Contribution of a VersaTile used as a combinatorial module
0.207
PAC8
Average contribution of a routing net
0.7
PAC9
Contribution of an I/O input pin (standard-dependent)
PAC10
Contribution of an I/O output pin (standard-dependent)
PAC11
Average contribution of a RAM block during a read operation
25.00
PAC12
Average contribution of a RAM block during a write operation
30.00
PAC13
Dynamic contribution for PLL
2.70
Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power
calculator or SmartPower in Libero SoC software.
Table 2-16 Different Components Contributing to the Static Power Consumption in IGLOO Devices
For IGLOOe V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Parameter
Definition
Device Specific Static Power (mW)
AGLE600
AGLE3000
PDC1
Array static power in Active mode
PDC2
Array static power in Static (Idle) mode
PDC3
Array static power in Flash*Freeze mode
PDC4
Static PLL contribution
1.84
PDC5
Bank quiescent power (VCCI-dependent)
PDC6
I/O input pin static power (standard-dependent)
PDC7
I/O output pin static power (standard-dependent)
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