Revision 13 2-31 The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The re" />
參數(shù)資料
型號： AGLE600V2-FGG256
廠商： Microsemi SoC
文件頁數(shù)： 107/166頁
文件大小： 0K
描述： IC FPGA 1KB FLASH 600K 256-FBGA
標準包裝： 90
系列： IGLOOe
邏輯元件/單元數(shù)： 13824
RAM 位總計： 110592
輸入/輸出數(shù)： 165
門數(shù)： 600000
電源電壓： 1.14 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 256-LBGA
供應商設備封裝： 256-FPBGA（17x17）
IGLOOe Low Power Flash FPGAs
Revision 13
2-31
The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The
reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months
to cause a reliability concern. The I/O design does not contain any short circuit protection, but such
protection would only be needed in extremely prolonged stress conditions.
Table 2-31 Duration of Short Circuit Event before Failure
Temperature
Time before Failure
–40°C
> 20 years
0°C
> 20 years
25°C
> 20 years
70°C
5 years
85°C
2 years
100°C
6 months
Table 2-32 Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode)
240 mV
2.5 V LVCMOS (Schmitt trigger mode)
140 mV
1.8 V LVCMOS (Schmitt trigger mode)
80 mV
1.5 V LVCMOS (Schmitt trigger mode)
60 mV
1.2 V LVCMOS (Schmitt trigger mode)
40 mV
Table 2-33 I/O Input Rise Time, Fall Time, and Related I/O Reliability*
Input Buffer
Input Rise/Fall Time
(min.)
Input Rise/Fall Time (max.)
Reliability
LVTTL/LVCMOS (Schmitt trigger
disabled)
No requirement
10 ns*
20 years
(100°C)
LVTTL/LVCMOS (Schmitt trigger
enabled)
No requirement
No requirement, but input noise
voltage
cannot
exceed
Schmitt
hysteresis.
20 years
(100°C)
HSTL/SSTL/GTL
No requirement
10 ns*
10 years
(100°C)
LVDS/B-LVDS/M-LVDS/LVPECL
No requirement
10 ns*
10 years
(100°C)
Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low,
then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the
rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity
evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.
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