參數(shù)資料
型號: AGLE600V2-FGG256C
元件分類: FPGA
英文描述: FPGA, 13824 CLBS, 600000 GATES, PBGA256
封裝: 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-256
文件頁數(shù): 116/156頁
文件大?。?/td> 5023K
代理商: AGLE600V2-FGG256C
IGLOOe DC and Switching Characteristics
2- 48
Advance v0.3
3.3 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to
3.3 V
Table 2-73 Minimum and Maximum DC Input and Output Levels
3.3 V GTL+
VIL
VIH
VOL
VOH
IOL IOH
IOSH
IOSL
IIL IIH
Drive Strength Min., V Max., V
Min., V
Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2
35 mA
–0.3
VREF – 0.1 VREF + 0.1
3.6
0.6
35 35
268
181
10
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-15 AC Loading
Table 2-74 AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF – 0.1
VREF + 0.1
1.0
1.5
10
* Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points.
Test Point
10 pF
25
GTL+
VTT
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