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| 型號(hào)： | AGLE600V5-FFG256C |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 13824 CLBS, 600000 GATES, PBGA256 |
| 封裝： | 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-256 |
| 文件頁(yè)數(shù)： | 7/156頁(yè) |
| 文件大?。?/td> | 5023K |
| 代理商： | AGLE600V5-FFG256C |
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IGLOOe DC and Switching Characteristics
2- 90
Advance v0.3
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be
driven and conditioned internally by the CCC module. For more details on clock conditioning
capabilities, refer to the "Clock Conditioning Circuits" section on page 2-92. Table 2-131 and
Table 2-133 present minimum and maximum global clock delays within the device. Minimum and
maximum delays are measured with minimum and maximum loading.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-131 AGLE600 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input LOW Delay for Global Clock
1.48
1.82
ns
tRCKH
Input HIGH Delay for Global Clock
1.52
1.94
ns
tRCKMPWH
Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL
Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.42
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-132 AGLE3000 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input LOW Delay for Global Clock
2.00
2.34
ns
tRCKH
Input HIGH Delay for Global Clock
2.09
2.51
ns
tRCKMPWH
Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL
Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.42
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGLE600V5-FFG484C | FPGA, 13824 CLBS, 600000 GATES, PBGA256 |
| AGLE600V5-FFGG256C | FPGA, 13824 CLBS, 600000 GATES, PBGA256 |
| AGLE600V5-FFGG484C | FPGA, 13824 CLBS, 600000 GATES, PBGA484 |
| AGLE600V5-FG256C | FPGA, 13824 CLBS, 600000 GATES, PBGA256 |
| AGLE600V5-FG484C | FPGA, 13824 CLBS, 600000 GATES, PBGA484 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGLE600V5-FFG484 | 制造商:Microsemi Corporation 功能描述:FPGA IGLOOE 600K GATES 130NM 1.5V 484FBGA - Trays |
| AGLE600V5-FFG896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V5-FFG896ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V5-FFG896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V5-FFG896PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
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