參數(shù)資料
型號： AGLE600V5-FGG484C
元件分類： FPGA
英文描述： FPGA, 13824 CLBS, 600000 GATES, PBGA484
封裝： 23 X 23 MM, 2.23 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, FBGA-484
文件頁數(shù)： 153/156頁
文件大?。?/td> 5023K
代理商： AGLE600V5-FGG484C
IGLOOe DC and Switching Characteristics
2- 82
Advance v0.3
Timing Characteristics
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Table 2-125 Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std.
Units
tDDROCLKQ
Clock-to-Out of DDR for Output DDR
1.07
ns
tDDROSUD1
Data_F Data Setup for Output DDR
0.67
ns
tDDROSUD2
Data_R Data Setup for Output DDR
0.67
ns
tDDROHD1
Data_F Data Hold for Output DDR
0.00
ns
tDDROHD2
Data_R Data Hold for Output DDR
0.00
ns
tDDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
1.38
ns
tDDROREMCLR
Asynchronous Clear Removal Time for Output DDR
0.00
ns
tDDRORECCLR
Asynchronous Clear Recovery Time for Output DDR
0.23
ns
tDDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.19
ns
tDDROCKMPWH
Clock Minimum Pulse Width HIGH for the Output DDR
0.31
ns
tDDROCKMPWL
Clock Minimum Pulse Width LOW for the Output DDR
0.28
ns
FDDOMAX
Maximum Frequency for the Output DDR
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating
values.
Table 2-126 Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC =1.14V
Parameter
Description
Std.
Units
tDDROCLKQ
Clock-to-Out of DDR for Output DDR
1.60
ns
tDDROSUD1
Data_F Data Setup for Output DDR
1.09
ns
tDDROSUD2
Data_R Data Setup for Output DDR
1.16
ns
tDDROHD1
Data_F Data Hold for Output DDR
0.00
ns
tDDROHD2
Data_R Data Hold for Output DDR
0.00
ns
tDDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
1.99
ns
tDDROREMCLR
Asynchronous Clear Removal Time for Output DDR
0.00
ns
tDDRORECCLR
Asynchronous Clear Recovery Time for Output DDR
0.24
ns
tDDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.19
ns
tDDROCKMPWH
Clock Minimum Pulse Width HIGH for the Output DDR
0.31
ns
tDDROCKMPWL
Clock Minimum Pulse Width LOW for the Output DDR
0.28
ns
FDDOMAX
Maximum Frequency for the Output DDR
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-6 for derating
values.
相關(guān)PDF資料
PDF描述
ACBQ20TTEB270K/390M RC NETWORK, BUSSED, 1W, 27ohm, 20V, 0.000039uF, SURFACE MOUNT, 20
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGLE600V5-FGG484I 功能描述:IC FPGA 1KB FLASH 600K 484-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOOe 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標準包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計:6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
AGLE600V5-FGG896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FGG896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FGG896I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
AGLE600V5-FGG896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology
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