參數(shù)資料
型號： AGLN030V2-ZFCS81
元件分類： FPGA
英文描述： FPGA, PBGA81
封裝： 5 X 5 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, CSP-81
文件頁數(shù)： 23/114頁
文件大小： 3991K
代理商： AGLN030V2-ZFCS81
IGLOO nano DC and Switching Characteristics
2- 2
A d vance v0.2
Table 2-2
Recommended Operating Conditions 1
Symbol
Parameter
Extended Commercial
Industrial
Units
TA
Ambient temperature
–20 to +70 2
–40 to +85 2
°C
TJ
Junction temperature
–20 to + 85 2
–40 to +100 2
°C
VCC
1.5 V DC core supply voltage3
1.425 to 1.575
V
1.2 V–1.5 V wide range core voltage4
1.14 to 1.575
V
VJTAG
JTAG DC voltage
1.425 to 3.6
V
VPUMP
5
Programming voltage Programming mode
3.15 to 3.45
V
Operation
0 to 3.45
V
VCCPLL
6
Analog power supply
(PLL)
1.5 V DC core supply voltage3
1.425 to 1.575
V
1.2 V–1.5 V wide range core
supply voltage4
1.14 to 1.575
V
VCCI
and
VMV 7,9
1.2 V DC supply voltage 4
1.14 to 1.26
V
1.2 V DC wide range supply voltage 4
1.14 to 1.575
V
1.5 V DC supply voltage
1.425 to 1.575
1.8 V DC supply voltage
1.7 to 1.9
V
2.5 V DC supply voltage
2.3 to 2.7
V
3.3 V DC supply voltage
3.0 to 3.6
V
3.3 V DC wide range supply voltage 8
2.7 to 3.6
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel
recommends that the user follow best design practices using Actel’s timing and power simulation tools.
3. For IGLOO nano V5 devices
4. For IGLOO nano V2 devices only, operating at VCCI ≥ VCC
5. VPUMP can be left floating during operation (not programming mode).
6. VCCPLL pins should be tied to VCC pins. See Pin Descriptions for further information.
7. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information.
8. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation.
9. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each
I/O standard are given in Table 2-20 on page 2-19. VCCI should be at the same voltage within a given I/O
bank.
Table 2-3
Flash Programming Limits – Retention, Storage, and Operating Temperature1
Product Grade Programming Cycles
Program Retention
(biased/unbiased)
Maximum Storage
Temperature TSTG (°C)
2
Maximum Operating Junction
Temperature TJ (°C)
2
Commercial
500
20 years
110
100
Industrial
500
20 years
110
100
Notes:
1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.
2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device
operating conditions and absolute limits.
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