參數(shù)資料
型號(hào): AGLN030V2-ZFQN48
元件分類: FPGA
英文描述: FPGA, PQCC48
封裝: 6 X 6 MM, 0.90 HEIGHT, 0.40 MM PITCH, QFN-48
文件頁數(shù): 33/114頁
文件大小: 3991K
代理商: AGLN030V2-ZFQN48
IGLOO nano DC and Switching Characteristics
Ad vance v0.2
2-11
Table 2-16 Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices
For IGLOO nano V2 Devices, 1.2 V Core Supply Voltage
Parameter
Definition
Device-Specific Dynamic Power (W/MHz)
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
PAC1
Clock contribution of a Global Rib
7.07
5.96
PAC2
Clock contribution of a Global Spine
1.01
0.52
0.26
PAC3
Clock contribution of a VersaTile
row
0.52
PAC4
Clock contribution of a VersaTile
used as a sequential module
0.07
PAC5
First contribution of a VersaTile used
as a sequential module
0.045
PAC6
Second contribution of a VersaTile
used as a sequential module
0.186
PAC7
Contribution of a VersaTile used as a
combinatorial module
0.11
PAC8
Average contribution of a routing
net
0.45
PAC9
Contribution of an I/O input pin
(standard-dependent)
PAC10
Contribution of an I/O output pin
(standard-dependent)
PAC11
Average contribution of a RAM
block during a read operation
25.00
N/A
PAC12
Average contribution of a RAM
block during a write operation
30.00
N/A
PAC13
Dynamic contribution for PLL
2.10
N/A
Table 2-17 Different Components Contributing to the Static Power Consumption in IGLOO nano Devices
For IGLOO nano V2 Devices, 1.2 V Core Supply Voltage
Parameter
Definition
Device-Specific Static Power (mW)
AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010
PDC1
Array static power in Active mode
PDC2
Array static power in Static (Idle)
mode
PDC3
Array static power in Flash*Freeze
mode
PDC4
2
Static PLL contribution
0.90
N/A
PDC5
Bank quiescent power
(VCCI-dependent)
Notes:
1. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power
spreadsheet calculator or the SmartPower tool in Actel Libero IDE.
2. Minimum contribution of the PLL when running at lowest frequency.
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