參數(shù)資料
型號： AGLN030V2-ZFQN68
元件分類： FPGA
英文描述： FPGA, PQCC68
封裝： 8 X 8 MM, 0.90 HEIGHT, 0.40 MM PITCH, QFN-68
文件頁數(shù)： 2/114頁
文件大小： 3991K
代理商： AGLN030V2-ZFQN68
IGLOO nano Device Overview
1- 6
A d vance v0.4
Flash*Freeze Technology
The IGLOO nano device has an ultra-low-power static mode, called Flash*Freeze mode, which
retains all SRAM and register information and can still quickly return to normal operation.
Flash*Freeze technology enables the user to quickly (within 1 s) enter and exit Flash*Freeze mode
by activating the Flash*Freeze pin while all power supplies are kept at their original values. I/Os,
global I/Os, and clocks can still be driven and can be toggling without impact on power
consumption, and the device retains all core registers, SRAM information, and I/O states. I/Os can
be individually configured to either hold their previous state or be tristated during Flash*Freeze
mode.
Alternatively, I/Os can be set to a specific state using weak pull-up or pull-down I/O attribute
configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device
consumes as little as 2 W in this mode.
Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the
power management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to
decide when it is safe to transition to this mode. Refer to Figure 1-5 for an illustration of
entering/exiting Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if
Flash*Freeze mode usage is not planned.
VersaTiles
The IGLOO nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS
core tiles. The IGLOO nano VersaTile supports the following:
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Refer to Figure 1-6 for VersaTile configurations.
Figure 1-5 IGLOO nano Flash*Freeze Mode
Actel IGLOO Nano
FPGA
Flash*Freeze
Mode Control
Flash*Freeze Pin
Figure 1-6 VersaTile Configurations
X1
Y
X2
X3
LUT-3
Data
Y
CLK
Enable
CLR
D-FF
Data
Y
CLK
CLR
D-FF
LUT-3 Equivalent
D-Flip-Flop with Clear or Set
Enable D-Flip-Flop with Clear or Set
相關(guān)PDF資料
PDF描述
AGLN030V2-ZFQNG48 FPGA, PQCC48
AGLN030V2-ZFQNG68 FPGA, PQCC68
AGLN030V2-ZFUC81 FPGA, PBGA81
AGLN030V2-ZFUCG81 FPGA, PBGA81
AGLN030V2-ZFVQ100 FPGA, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AGLN030V2-ZQNG48 功能描述:IC FPGA NANO 1KB 30K 48-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
AGLN030V2-ZQNG48I 功能描述:IC FPGA NANO 1KB 30K 48-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
AGLN030V2-ZQNG68 功能描述:IC FPGA NANO 1KB 30K 68-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
AGLN030V2-ZQNG68I 功能描述:IC FPGA NANO 1KB 30K 68-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
AGLN030V2-ZUCG81 功能描述:IC FPGA NANO 1KB 30K 81-UCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
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