參數(shù)資料
型號: AGLN030V2-ZFQNG48
元件分類: FPGA
英文描述: FPGA, PQCC48
封裝: 6 X 6 MM, 0.90 HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, QFN-48
文件頁數(shù): 90/114頁
文件大?。?/td> 3991K
代理商: AGLN030V2-ZFQNG48
IGLOO nano DC and Switching Characteristics
Ad vance v0.2
2-63
1.2 V DC Core Voltage
Table 2-86 AGLN010 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input LOW Delay for Global Clock
TBD
ns
tRCKH
Input HIGH Delay for Global Clock
TBD
ns
tRCKMPWH
Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL
Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
TBD
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
Table 2-87 AGLN015 Global Resource
Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
Description
Std.
Units
Min.1
Max.2
tRCKL
Input LOW Delay for Global Clock
TBD
ns
tRCKH
Input HIGH Delay for Global Clock
TBD
ns
tRCKMPWH
Minimum Pulse Width HIGH for Global Clock
ns
tRCKMPWL
Minimum Pulse Width LOW for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
TBD
ns
FRMAX
Maximum Frequency for Global Clock
MHz
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating
values.
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