參數(shù)資料
型號: AGLN060V2-ZVQ100
廠商: Microsemi SoC
文件頁數(shù): 8/150頁
文件大小: 0K
描述: IC FPGA NANO 1KB 60K 100VQFP
標準包裝: 90
系列: IGLOO nano
邏輯元件/單元數(shù): 1536
RAM 位總計: 18432
輸入/輸出數(shù): 71
門數(shù): 60000
電源電壓: 1.14 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -20°C ~ 70°C
封裝/外殼: 100-TQFP
供應商設備封裝: 100-VQFP(14x14)
Revision 17
3-1
3 – Pin Descriptions
Supply Pins
GND
Ground
Ground supply voltage to the core, I/O outputs, and I/O logic.
GNDQ
Ground (quiet)
Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is
decoupled from the simultaneous switching noise originated from the output buffer ground domain. This
minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always
be connected to GND on the board.
VCC
Core Supply Voltage
Supply voltage to the FPGA core, nominally 1.5 V for IGLOO nano V5 devices, and 1.2 V or 1.5 V for
IGLOO nano V2 devices. VCC is required for powering the JTAG state machine in addition to VJTAG.
Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG
must remain powered to allow JTAG signals to pass through the device.
VCCIBx
I/O Supply Voltage
Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to
eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a
separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.2 V,
1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI
pins tied to GND.
VMVx
I/O Supply Voltage (quiet)
Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the
VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within
the package and improves input signal integrity. Each bank must have at least one VMV connection, and
no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to
provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.2 V, 1.5 V, 1.8 V,
2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND.
VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be
connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1,
etc.).
VCCPLA/B/C/D/E/F
PLL Supply Voltage
Supply voltage to analog PLL, nominally 1.5 V or 1.2 V.
When the PLLs are not used, the Microsemi Designer place-and-route tool automatically disables the
unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to
ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple
VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning
Circuits in IGLOO and ProASIC3 Devices" chapter in the IGLOO nano FPGA Fabric User’s Guide for a
complete board solution for the PLL analog power supply and ground.
There is one VCCPLF pin on IGLOO nano devices.
VCOMPLA/B/C/D/E/F
PLL Ground
Ground to analog PLL power supplies. When the PLLs are not used, the Microsemi Designer place-and-
route tool automatically disables the unused PLLs to lower power consumption. The user should tie
unused VCCPLx and VCOMPLx pins to ground.
There is one VCOMPLF pin on IGLOO nano devices.
VJTAG
JTAG Supply Voltage
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank
gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG
相關PDF資料
PDF描述
AGL060V2-VQ100 IC FPGA 1KB FLASH 60K 100-VQFP
EP4CE6E22C9LN IC CYCLONE IV FPGA 6K 144EQFP
BR24T64FVT-WE2 IC EEPROM I2C 64K 400KHZ 8-TSSOP
BR24T64FVM-WTR IC EEPROM I2C 64K 400KHZ 8-MSOP
AYM30DTBD-S189 CONN EDGECARD 60POS R/A .156 SLD
相關代理商/技術參數(shù)
參數(shù)描述
AGLN060V2-ZVQ100I 功能描述:IC FPGA NANO 1KB 60K 100VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:IGLOO nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應商設備封裝:289-CSP(14x14)
AGLN060V2-ZVQG100 功能描述:IC FPGA NANO 1KB 60K 100VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:IGLOO nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應商設備封裝:289-CSP(14x14)
AGLN060V2-ZVQG100I 功能描述:IC FPGA NANO 1KB 60K 100VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:IGLOO nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應商設備封裝:289-CSP(14x14)
AGLN060V5-CSG81 功能描述:IC FPGA 60K 1.5V CSP81 RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:IGLOO nano 標準包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應商設備封裝:388-FPBGA(23x23) 其它名稱:220-1241
AGLN060V5-CSG81I 功能描述:IC FPGA NANO 1KB 60K 81-CSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:IGLOO nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA,CSBGA 供應商設備封裝:289-CSP(14x14)