參數資料
型號： AGLN125V5-FQN100
元件分類： FPGA
英文描述： FPGA, PBCC100
封裝： 8 X 8 MM, 0.85 HEIGHT, 0.50 MM PITCH, QFN-100
文件頁數： 35/114頁
文件大?。?/td> 3991K
代理商： AGLN125V5-FQN100
IGLOO nano DC and Switching Characteristics
Ad vance v0.2
2-13
Combinatorial Cells Contribution—PC-CELL
PC-CELL = NC-CELL*
α
1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on
FCLK is the global clock signal frequency.
Routing Net Contribution—PNET
PNET = (NS-CELL + NC-CELL) *
α
1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-18 on
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—PINPUTS
PINPUTS = NINPUTS *
α
2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-14.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—POUTPUTS
POUTPUTS = NOUTPUTS *
α
2 / 2 *
β
1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-18 on page 2-14.
β
1 is the I/O buffer enable rate—guidelines are provided in Table 2-19 on page 2-14.
FCLK is the global clock signal frequency.
RAM Contribution—PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK *
β
2 + PAC12 * NBLOCK * FWRITE-CLOCK *
β
3
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
β
2 is the RAM enable rate for read operations.
FWRITE-CLOCK is the memory write clock frequency.
β
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-19
PLL Contribution—PPLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.
1
1.
If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its
corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.
相關PDF資料
PDF描述
AGLN125V5-FQNG100 FPGA, PBCC100
AGLN125V5-FVQ100 FPGA, PQFP100
AGLN125V5-FVQG100 FPGA, PQFP100
AGLN125V5-QN100I FPGA, PBCC100
AGLN125V5-QN100 FPGA, PBCC100
相關代理商/技術參數
參數描述
AGLN125V5-QNG100 制造商:Microsemi Corporation 功能描述:FPGA IGLOO NANO FAMILY 125K GATES 130NM (CMOS) TECHNOLOGY 1. - Trays
AGLN125V5-QNG100I 制造商:Microsemi Corporation 功能描述:FPGA IGLOO NANO FAMILY 125K GATES 130NM (CMOS) TECHNOLOGY 1. - Trays
AGLN125V5-VQ100 功能描述:IC FPGA NANO 1KB 125K 100VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:IGLOO nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數:- 邏輯元件/單元數:792 RAM 位總計:- 輸入/輸出數:120 門數:30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14）
AGLN125V5-VQ100I 功能描述:IC FPGA NANO 1KB 125K 100VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:IGLOO nano 標準包裝:152 系列:IGLOO PLUS LAB/CLB數:- 邏輯元件/單元數:792 RAM 位總計:- 輸入/輸出數:120 門數:30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14）
AGLN125V5-VQG100 功能描述:IC FPGA 125K 1.5V 100VTQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現場可編程門陣列） 系列:IGLOO nano 標準包裝:24 系列:ECP2 LAB/CLB數:1500 邏輯元件/單元數:12000 RAM 位總計:226304 輸入/輸出數:131 門數:- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:208-BFQFP 供應商設備封裝:208-PQFP（28x28）
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