參數(shù)資料
型號: AGLP060V2-CSG201I
元件分類: FPGA
英文描述: FPGA, 1584 CLBS, 60000 GATES, PBGA201
封裝: 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-201
文件頁數(shù): 59/128頁
文件大?。?/td> 4383K
代理商: AGLP060V2-CSG201I
IGLOO PLUS DC and Switching Characteristics
2- 22
R e v i sio n 1 1
Table 2-25 Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade,
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
I/
O
S
tan
dard
Dr
ive
S
trength
Eq
uivalen
tSo
ft
ware
De
fault
Drive
S
trength
Option
1
Slew
Rat
e
Ca
p
acitive
Lo
ad
(p
F)
Ex
te
rn
al
R
e
si
st
or
(
Ω
)
t DO
UT
t DP
t DI
N
t PY
t PYS
t EOUT
t ZL
t ZH
t LZ
t HZ
Unit
s
3.3 V LVTTL /
3.3 V LVCMOS
12 mA 12 mA High 5 pF
0.97
1.76 0.18 0.85 1.15 0.66 1.80 1.39 2.20 2.64
ns
3.3 V LVCMOS
Wide Range2
100 A 12 mA High 5 pF –
0.97
2.47 0.18 1.18 1.64 0.66 2.48 1.91 3.16 3.76
ns
2.5 V LVCMOS
12 mA 12 mA High 5 pF
0.97
1.77 0.18 1.06 1.22 0.66 1.81 1.51 2.22 2.56
ns
1.8 V LVCMOS
8 mA
High 5 pF
0.97
2.00 0.18 1.00 1.43 0.66 2.04 1.76 2.29 2.55
ns
1.5 V LVCMOS
4 mA
High 5 pF
0.97
2.29 0.18 1.16 1.62 0.66 2.33 2.00 2.37 2.57
ns
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 A drive strength only. The configuration will not operate at the
equivalent software default drive strength. These values are for normal ranges only.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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