參數(shù)資料
型號: AGLP060V2-VQG176I
元件分類: FPGA
英文描述: FPGA, 1584 CLBS, 60000 GATES, PQFP176
封裝: 20 X 20 MM, 1 MM HEIGHT, 0.4 MM PITCH, VQFP-176
文件頁數(shù): 45/128頁
文件大?。?/td> 4383K
代理商: AGLP060V2-VQG176I
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2-9
Power per I/O Pin
Table 2-13 Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
VCCI (V)
Dynamic Power
PAC9 (W/MHz) 1
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3
16.26
3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger
3.3
18.95
3.3 V LVCMOS Wide Range2
3.3
16.26
3.3 V LVCMOS Wide Range2 – Schmitt Trigger
3.3
18.95
2.5 V LVCMOS
2.5
4.59
2.5 V LVCMOS – Schmitt Trigger
2.5
6.01
1.8 V LVCMOS
1.8
1.61
1.8 V LVCMOS – Schmitt Trigger
1.8
1.70
1.5 V LVCMOS (JESD8-11)
1.5
0.96
1.5 V LVCMOS (JESD8-11) – Schmitt Trigger
1.5
0.90
1.2 V LVCMOS3
1.2
0.55
1.2 V LVCMOS3 – Schmitt Trigger
1.2
0.47
1.2 V LVCMOS Wide Range3
1.2
0.55
1.2 V LVCMOS Wide Range3 – Schmitt Trigger
1.2
0.47
Notes:
1. PAC9 is the total dynamic power measured on VCCI.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. Applicable for IGLOO PLUS V2 devices only, operating at VCCI
≥ VCC.
Table 2-14 Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
CLOAD (pF)
VCCI (V)
Dynamic Power
PAC10 (W/MHz)2
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
5
3.3
127.11
3.3 V LVCMOS Wide Range3
5
3.3
127.11
2.5 V LVCMOS
5
2.5
70.71
1.8 V LVCMOS
5
1.8
35.57
1.5 V LVCMOS (JESD8-11)
5
1.5
24.30
1.2 V LVCMOS4
51.2
15.22
1.2 V LVCMOS Wide Range4
51.2
15.22
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PAC10 is the total dynamic power measured on VCCI.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable for IGLOO PLUS V2 devices only, operating at VCCI
≥ VCC.
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AGLP060V2-VQG176 FPGA, 1584 CLBS, 60000 GATES, PQFP176
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