參數(shù)資料
型號(hào): AGLP060V2CSG201
元件分類: FPGA
英文描述: FPGA, 1584 CLBS, 60000 GATES, PBGA201
封裝: 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-201
文件頁數(shù): 67/128頁
文件大?。?/td> 4383K
代理商: AGLP060V2CSG201
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 29
3.3 V LVCMOS Wide Range
Table 2-40 Minimum and Maximum DC Input and Output Levels
3.3 V LVCMOS
Wide Range
Equivalent
Software
Default
Drive
Strength
Option1
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL
2
IIH
3
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VA
A
Max.
A4
Max.
A4
A5 A5
100 A
2 mA
–0.3
0.8
2
3.6
0.2
VDD – 0.2 100 100
25
27
10
100 A
4 mA
–0.3
0.8
2
3.6
0.4
VDD – 0.2 100 100
25
27
10
100 A
6 mA
–0.3
0.8
2
3.6
0.4
VDD – 0.2 100 100
51
54
10
100 A
8 mA
–0.3
0.8
2
3.6
0.4
VDD – 0.2 100 100
51
54
10
100 A
12 mA
–0.3
0.8
2
3.6
0.4
VDD – 0.2 100
100
103
109
10
100 A
16 mA
–0.3
0.8
2
3.6
0.4
VDD – 0.2 100 100
103
109
10
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < V CCI. Input current is
larger when operating outside recommended ranges.
4. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
5. Currents are measured at 85°C junction temperature.
6. Software default selection highlighted in gray.
Table 2-41 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
CLOAD (pF)
03.3
1.4
5
* Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.
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