參數(shù)資料
型號: AGLP060V5-CS201
元件分類: FPGA
英文描述: FPGA, 1584 CLBS, 60000 GATES, PBGA201
封裝: 8 X 8 MM, 0.89 MM HEIGHT, 0.5 MM PITCH, CSP-201
文件頁數(shù): 60/128頁
文件大?。?/td> 4383K
代理商: AGLP060V5-CS201
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 23
Table 2-26 Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V
I/
O
S
tan
dard
Dr
ive
S
trength
Eq
uivalen
tSo
ft
ware
De
fault
Drive
S
trength
Option
1
Slew
Rat
e
Ca
p
acitive
Lo
ad
(p
F)
Ex
te
rn
al
R
e
si
st
or
(
Ω
)
t DO
UT
t DP
t DI
N
t PY
)
t PYS
t EOUT
t ZL
t ZH
t LZ
t HZ
Unit
s
3.3 V LVTTL /
3.3 V LVCMOS
12 mA 12 mA High 5 pF
0.98 2.31 0.19 0.99 1.37 0.67 2.34 1.86 2.65 3.38
ns
3.3 V LVCMOS
Wide Range2
100 A 12 mA High 5 pF
0.98 3.21 0.19 1.32 1.92 0.67 3.21 2.52 3.73 4.73
ns
2.5 V LVCMOS
12 mA 12 mA High 5 pF
0.98 2.29 0.19 1.19 1.40 0.67 2.32 1.94 2.65 3.27
ns
1.8 V LVCMOS
8 mA 8 mA High 5 pF
0.98 2.45 0.19 1.12 1.61 0.67 2.48 2.16 2.71 3.16
ns
1.5 V LVCMOS
4 mA 4 mA High 5 pF
0.98 2.71 0.19 1.26 1.80 0.67 2.75 2.39 2.78 3.15
ns
1.2 V LVCMOS
2 mA 2 mA High 5 pF
0.98 3.380.191.572.340.673.262.782.99 3.24
ns
1.2 V LVCMOS
Wide Range3
100 A 2 mA High 5 pF
0.98 3.38 0.19 1.57 2.34 0.67 3.26 2.78 2.99 3.24
ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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