參數(shù)資料
型號(hào): AGLP060V5-CSG201
元件分類: FPGA
英文描述: FPGA, 1584 CLBS, 60000 GATES, PBGA201
封裝: 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-201
文件頁數(shù): 47/128頁
文件大?。?/td> 4383K
代理商: AGLP060V5-CSG201
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 11
Table 2-16 Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage
Parameter
Definition
Device-Specific Static Power (mW)
AGLP125
AGLP060
AGLP030
PDC1
Array static power in Active mode
PDC2
Array static power in Static (Idle) mode
PDC3
Array static power in Flash*Freeze mode
PDC4
Static PLL contribution
1.841
PDC5
Bank quiescent power (VCCI-dependent)
Notes:
1. This is the minimum contribution of the PLL when operating at lowest frequency.
2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator
or the SmartPower tool in Actel Libero Integrated Design Environment (IDE) software.
Table 2-17 Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices
For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage
Parameter
Definition
Device-Specific Dynamic Power
(W/MHz)
AGLP125
AGLP060 AGLP030
PAC1
Clock contribution of a Global Rib
7.07
5.96
PAC2
Clock contribution of a Global Spine
0.52
0.26
PAC3
Clock contribution of a VersaTile row
0.52
PAC4
Clock contribution of a VersaTile used as a sequential module
0.07
PAC5
First contribution of a VersaTile used as a sequential module
0.045
PAC6
Second contribution of a VersaTile used as a sequential module
0.186
PAC7
Contribution of a VersaTile used as a combinatorial module
0.11
PAC8
Average contribution of a routing net
0.45
PAC9
Contribution of an I/O input pin (standard-dependent)
PAC10
Contribution of an I/O output pin (standard-dependent)
PAC11
Average contribution of a RAM block during a read operation
25.00
PAC12
Average contribution of a RAM block during a write operation
30.00
PAC13
Dynamic contribution for PLL
2.10
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