參數(shù)資料
型號: AGLP060V5-CSG289
元件分類: FPGA
英文描述: FPGA, 1584 CLBS, 60000 GATES, PBGA289
封裝: 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-289
文件頁數(shù): 110/128頁
文件大?。?/td> 4383K
代理商: AGLP060V5-CSG289
IGLOO PLUS DC and Switching Characteristics
2- 68
R e v i sio n 1 1
Timing Characteristics
1.5 V DC Core Voltage
Table 2-92 RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std. Units
tAS
Address setup time
0.69
ns
tAH
Address hold time
0.13
ns
tENS
REN_B, WEN_B setup time
0.68
ns
tENH
REN_B, WEN_B hold time
0.13
ns
tBKS
BLK_B setup time
1.37
ns
tBKH
BLK_B hold time
0.13
ns
tDS
Input data (DI) setup time
0.59
ns
tDH
Input data (DI) hold time
0.30
ns
tCKQ1
Clock High to new data valid on DO (output retained, WMODE = 0)
2.94
ns
Clock High to new data valid on DO (flow-through, WMODE = 1)
2.55
ns
tCKQ2
Clock High to new data valid on DO (pipelined)
1.51
ns
tC2CWWL
Address collision clk-to-clk delay for reliable write after write on same address – applicable
to closing edge
0.29
ns
tC2CRWH
Address collision clk-to-clk delay for reliable read access after write on same address –
applicable to opening edge
0.24
ns
tC2CWRH
Address collision clk-to-clk delay for reliable write access after read on same address –
applicable to opening edge
0.40
ns
tRSTBQ
RESET_B Low to data out Low on DO (flow-through)
1.72
ns
RESET_B Low to data out Low on DO (pipelined)
1.72
ns
tREMRSTB
RESET_B removal
0.51
ns
tRECRSTB
RESET_B recovery
2.68
ns
tMPWRSTB
RESET_B minimum pulse width
0.68
ns
tCYC
Clock cycle time
6.24
ns
FMAX
Maximum frequency
160
MHz
Note:
For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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