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| 型號(hào)： | AGLP060V5-VQG176I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1584 CLBS, 60000 GATES, PQFP176 |
| 封裝： | 20 X 20 MM, 1 MM HEIGHT, 0.4 MM PITCH, VQFP-176 |
| 文件頁(yè)數(shù)： | 102/128頁(yè) |
| 文件大?。?/td> | 4383K |
| 代理商： | AGLP060V5-VQG176I |
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IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 61
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-90 IGLOO PLUS CCC/PLL Specification
For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage
Parameter
Min.
Typ.
Max.
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
250
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
250
MHz
Delay Increments in Programmable Delay Blocks 1, 2
360
ps
Number of Programmable Values in Each Programmable Delay Block
32
Serial Clock (SCLK) for Dynamic PLL3,4
Input Cycle-to-Cycle Jitter (peak magnitude)
100
MHz
Acquisition Time
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter5
LockControl = 0
2.5
LockControl = 1
1.5
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 1 1, 2
1.25
15.65
ns
Delay Range in Block: Programmable Delay 2 1, 2
0.469
15.65
ns
Delay Range in Block: Fixed Delay 1, 2
3.5
ns
VCO Output Peak-to-Peak Period Jitter FCCC_OUT
6
Maximum Peak-to-Peak Period Jitter6,7,8
SSO
≤ 2 SSO ≤ 4
SSO
≤ 8
SSO
≤ 16
0.75 MHz to 50 MHz
0.50%
0.60%
0.80%
1.20%
50 MHz to 250 MHz
2.50%
4.00%
6.00%
12.00%
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings.
2. TJ = 25°C, VCC = 1.5 V
3. Maximum value obtained for a STD speed grade device in Worst Case Commercial Conditions. For specific junction
temperature and voltage supply, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values.
4. The AGLP030 device does not support a PLL.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying
the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider
settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output
divider settings.
7. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate, VCC/VCCPLL = 1.14 V,
VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load.
8. SSO are outputs that are synchronous to a single clock domain and have clock-to-out times that are within ±200 ps of
each other.Switching I/Os are placed outside of the PLL bank. Refer to the "ProASIC3/E SSO and Pin Placement
Guidelines" chapter of the ProASIC3 FPGA Fabric User’s Guide.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGLP060-V5VQG289 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP060-V5VQG289ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP060-V5VQG289I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP060-V5VQG289PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP125V2-CS281 | 功能描述:IC FPGA IGLOO PLUS 125K 281-CSP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:IGLOO PLUS 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門(mén)數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
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