參數(shù)資料
型號(hào): AGLP125V5-CSG289
元件分類: FPGA
英文描述: FPGA, 3120 CLBS, 125000 GATES, PBGA289
封裝: 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-289
文件頁數(shù): 119/128頁
文件大?。?/td> 4383K
代理商: AGLP125V5-CSG289
IGLOO PLUS DC and Switching Characteristics
2- 76
R e v i sio n 1 1
1.2 V DC Core Voltage
Table 2-97 FIFO
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
Description
Std.
Units
tENS
REN_B, WEN_B Setup Time
3.44
ns
tENH
REN_B, WEN_B Hold Time
0.26
ns
tBKS
BLK_B Setup Time
0.30
ns
tBKH
BLK_B Hold Time
0.00
ns
tDS
Input Data (DI) Setup Time
1.30
ns
tDH
Input Data (DI) Hold Time
0.41
ns
tCKQ1
Clock High to New Data Valid on DO (flow-through)
5.67
ns
tCKQ2
Clock High to New Data Valid on DO (pipelined)
3.02
ns
tRCKEF
RCLK High to Empty Flag Valid
6.02
ns
tWCKFF
WCLK High to Full Flag Valid
5.71
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
22.17
ns
tRSTFG
RESET_B Low to Empty/Full Flag Valid
5.93
ns
tRSTAF
RESET_B Low to Almost Empty/Full Flag Valid
21.94
ns
tRSTBQ
RESET_B Low to Data Out Low on DO (flow-through)
3.41
ns
RESET_B Low to Data Out Low on DO (pipelined)
3.41
ns
tREMRSTB
RESET_B Removal
1.02
ns
tRECRSTB
RESET_B Recovery
5.48
ns
tMPWRSTB
RESET_B Minimum Pulse Width
1.18
ns
tCYC
Clock Cycle Time
10.90
ns
FMAX
Maximum Frequency for FIFO
92
MHz
Note:
For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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