參數(shù)資料
型號: AGLP125V5CS281I
元件分類: FPGA
英文描述: FPGA, 3120 CLBS, 125000 GATES, PBGA281
封裝: 10 X 10 MM, 1.05 MM HEIGHT, 0.5 MM PITCH, CSP-281
文件頁數(shù): 61/128頁
文件大?。?/td> 4383K
代理商: AGLP125V5CS281I
IGLOO PLUS DC and Switching Characteristics
2- 24
R e v i sio n 1 1
Detailed I/O DC Characteristics
Table 2-27 Input Capacitance
Symbol
Definition
Conditions
Min.
Max.
Units
CIN
Input capacitance
VIN = 0, f = 1.0 MHz
8
pF
CINCLK
Input capacitance on the clock pin
VIN = 0, f = 1.0 MHz
8
pF
Table 2-28 I/O Output Buffer Maximum Resistances 1
Standard
Drive Strength
RPULL-DOWN
(
Ω) 2
RPULL-UP
(
Ω) 3
3.3 V LVTTL / 3.3V LVCMOS
2 mA
100
300
4 mA
100
300
6 mA
50
150
8 mA
50
150
12 mA
25
75
16 mA
25
75
3.3 V LVCMOS Wide Range
100 A
Same as equivalent software default drive
2.5 V LVCMOS
2 mA
100
200
4 mA
100
200
6 mA
50
100
8 mA
50
100
12 mA
25
50
1.8 V LVCMOS
2 mA
200
225
4 mA
100
112
6 mA
50
56
8 mA
50
56
1.5 V LVCMOS
2 mA
200
224
4 mA
100
112
1.2 V LVCMOS
2 mA
157.5
163.8
1.2 V LVCMOS Wide Range4
100 A
157.5
163.8
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS model on the Actel website at http://www.actel.com/download/ibis/default.aspx.
2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec
3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec
4. Applicable to IGLOO PLUS V2 devices operating at VCCI
≥ VCC.
相關(guān)PDF資料
PDF描述
AGLP125V5CS281 FPGA, 3120 CLBS, 125000 GATES, PBGA281
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AGLP125V5CSG281I FPGA, 3120 CLBS, 125000 GATES, PBGA281
AGLP125V5CSG281 FPGA, 3120 CLBS, 125000 GATES, PBGA281
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