參數(shù)資料
型號: AGLP125V5CS289I
元件分類: FPGA
英文描述: FPGA, 3120 CLBS, 125000 GATES, PBGA289
封裝: 14 X 14 MM , 1.2 MM HEIGHT, 0.8 MM PITCH, CSP-289
文件頁數(shù): 81/128頁
文件大?。?/td> 4383K
代理商: AGLP125V5CS289I
IGLOO PLUS DC and Switching Characteristics
2- 42
R e v i sio n 1 1
Table 2-72 Parameter Definition and Measuring Nodes
Parameter Name
Parameter Definition
Measuring Nodes
(from, to)*
tOCLKQ
Clock-to-Q of the Output Data Register
H, DOUT
tOSUD
Data Setup Time for the Output Data Register
F, H
tOHD
Data Hold Time for the Output Data Register
F, H
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
L, DOUT
tOREMPRE
Asynchronous Preset Removal Time for the Output Data Register
L, H
tORECPRE
Asynchronous Preset Recovery Time for the Output Data Register
L, H
tOECLKQ
Clock-to-Q of the Output Enable Register
H, EOUT
tOESUD
Data Setup Time for the Output Enable Register
J, H
tOEHD
Data Hold Time for the Output Enable Register
J, H
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
I, EOUT
tOEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register
I, H
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
I, H
tICLKQ
Clock-to-Q of the Input Data Register
A, E
tISUD
Data Setup Time for the Input Data Register
C, A
tIHD
Data Hold Time for the Input Data Register
C, A
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
D, E
tIREMPRE
Asynchronous Preset Removal Time for the Input Data Register
D, A
tIRECPRE
Asynchronous Preset Recovery Time for the Input Data Register
D, A
* See Figure 2-12 on page 2-41 for more information.
相關PDF資料
PDF描述
AGLP125V5CS289 FPGA, 3120 CLBS, 125000 GATES, PBGA289
AGLP125V5CSG281I FPGA, 3120 CLBS, 125000 GATES, PBGA281
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AGLP125V5CSG289I FPGA, 3120 CLBS, 125000 GATES, PBGA289
AGLP125V5CSG289 FPGA, 3120 CLBS, 125000 GATES, PBGA289
相關代理商/技術參數(shù)
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