參數(shù)資料
型號: AGLP125V5CSG289I
元件分類: FPGA
英文描述: FPGA, 3120 CLBS, 125000 GATES, PBGA289
封裝: 14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-289
文件頁數(shù): 56/128頁
文件大?。?/td> 4383K
代理商: AGLP125V5CSG289I
IGLOO PLUS Low Power Flash FPGAs
Re vi s i on 11
2 - 19
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software
Settings
Table 2-21 Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial Conditions—Software Default Settings
I/O Standard
Drive
Strength
Equiv.
Software
Default
Drive
Strength
Option2
Slew
Rate
VIL
VIH
VOL
VOH
IOL
1 I
OH
1
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
3.3 V LVTTL /
3.3 V LVCMOS
12 mA
High –0.3
0.8
2
3.6
0.4
2.4
12
3.3 V LVCMOS
Wide Range3
100 A
12 mA
High –0.3
0.8
2
3.6
0.2
VDD 3 0.2
0.1 0.1
2.5 V LVCMOS
12 mA
High –0.3
0.7
1.7
3.6
0.7
1.7
12
1.8 V LVCMOS
8 mA
High –0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.45
VCCI – 0.45
8
1.5 V LVCMOS
4 mA
High –0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
4
1.2 V
LVCMOS4
2 mA
High –0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI
2
1.2 V LVCMOS
Wide Range4,5
100 A
2 mA
High –0.3 0.3 * VCCI
0.7 * VCCI
3.6
0.1
VCCI – 0.1
0.1 0.1
Notes:
1. Currents are measured at 85°C junction temperature.
2. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range are applicable to 100 A drive strength only. The configuration
will not operate at the equivalent software default drive strength. These values are for normal ranges only.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
4. Applicable to IGLOO PLUS V2 devices operating at VCCI VCC.
5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification.
相關(guān)PDF資料
PDF描述
AGLP125V5CSG289 FPGA, 3120 CLBS, 125000 GATES, PBGA289
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AGLP060V2-CS201 FPGA, 1584 CLBS, 60000 GATES, PBGA201
AGLP060V2-CS289I FPGA, 1584 CLBS, 60000 GATES, PBGA289
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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