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參數(shù)資料
| 型號(hào)： | AGM2416B |
| 廠商： | AZ Displays, Inc. |
| 英文描述： | SPECIFICATIONS FOR LIQUID CRYSTAL DISPLAY |
| 中文描述： | 規(guī)格液晶顯示器 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大小： | 1006K |
| 代理商： | AGM2416B |
AGM2412B
Page 3 of 12
AZ DISPLAYS, INC.
3.1 Pin Description
Segment Pin
Pin No.
1
2
3
4
5
6
7
8
Symbol
V0L
V12L
V34L
V5L
VSS
VSS
VDD
VDD
Function Description
Bias power supply pins for LCD drive voltage
Normally use the bias voltages set by a resistor divider
Ensure that voltages are set such that V
SS
V
5
< V
43
< V
12
< V
0
.
V
iL
and V
iR
(i = 0,12, 43, 5) must connect to an external power supply, and
supply regular voltage which is assigned by specification for each power pin
Ground
Logic power supply
9
DBLKB
Use as contrast control, use PWM signal as input. Connect to V
DD
for no
contrast control.
10
11
12
13
D0
D1
D2
D3
Data bus
14
XCK
Clock input pin for taking display data
* Data is read at the falling edge of the clock pulse.
15
DOFFB
Control input pin for output of non-select level
The input signal is level-shifted from logic voltage level to LCD drive voltage
level, and controls the LCD drive circuit.
When set to V
SS
level "L", the LCD drive output pins (Y
1
-Y
240
) are set to level
Vss.
When set to "L", the contents of the line latch are reset, but the display data
are read in the data latch regardless of the condition of DISPOFF. When the
DISPOFF function is canceled, the driver outputs non-select level (V
12
or V
43
),
then outputs the contents of the data latch at the next falling edge of the LP. At
that time, if DISPOFF removal time does not correspondto what is shown in AC
characteristics, it can not output the reading data correctly.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
16
LP
Latch pulse input pin for display data
Data is latched at the falling edge of the clock pulse.
17
FR
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage
level, and controls the LCD drive circuit.
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the line
latch output signal and the FR signal.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
Mode selection pin
When set to V
SS
level "L", 8-bit parallel input mode is set.
When set to V
DD
level "H", 4-bit parallel input mode is set.
Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD
DRIVE OUTPUT PINS" in Functional Operations.
Bias power supply pins for LCD drive voltage
18
MD
19
V5R
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| AGM2432B-FE-FBH-T | AZ DISPLAYS, INC. |
| AGM2432B | LCD MODULE |
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相關(guān)代理商/技術(shù)參數(shù) |
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| AGM2416B-FN-FBW | 制造商:AZDISPLAYS 制造商全稱:AZ Displays 功能描述:STANDARD CHIP-ON-GLASS DISPLAYS |
| AGM2432B | 制造商:AZDISPLAYS 制造商全稱:AZ Displays 功能描述:LCD MODULE |
| AGM2432B_07 | 制造商:AZDISPLAYS 制造商全稱:AZ Displays 功能描述:SPECIFICATIONS FOR LIQUID CRYSTAL DISPLAY |
| AGM2432B-FE-FBH-T | 制造商:AZDISPLAYS 制造商全稱:AZ Displays 功能描述:AZ DISPLAYS, INC. |
| AGM2432D | 制造商:AZDISPLAYS 制造商全稱:AZ Displays 功能描述:SPECIFICATIONS FOR LIQUID CRYSTAL DISPLAY |
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