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參數(shù)資料
| 型號： | AK2500B |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | RECEIVER, PDSO24 |
| 封裝： | SOP-24 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 78K |
| 代理商： | AK2500B |
ASAHI KASEI
[AK2500B]
MS0005-E-00
- 4 -
1999/12
PIN DESCRIPTION
No.
Pin Name
I/O
Function
1
IREF
O
Current reference output determined by the external resister.
External resistance 4.9 kohm(+/-1%) should be connected between this pin and
VSSA.
2
LOSTHR
I
Loss of Signal Threshold Control
The voltage forced on this pin controls the input loss-of-signal threshold. Three
settings are provided by forcing GND, VDD/2, or VDD at LOSTHR (see Table
6).
3
RLOL
O
Receive PLL Loss-of-Lock
Active High alarm. If the recovered clock frequency is larger than approximately
0.5% of EXCLK, RLOL alarm goes High.
4
RIN
I
Receive Input
Unbalanced analog receive input. The B3ZS receive signal is input to this pins.
Data and clock are recovered and output on RPDATA, RNDATA and RCLK.
5
VDDA
-
6
VDDA
-
Power Supply for the analog part. +3.3 volts.
7
RESET
I
Active low RESET. Pulled up to VDD with internal resister.
8
BREF
O
Bottom voltage reference level output.
An external capacitor (0.1
uF±20%) should be connected between this pin and
VSSA.
9
TREF
O
Top voltage reference level output.
An external capacitor (0.1
uF±20%) should be connected between this pin and
VSSA.
10
VSSA
-
Ground for the analog part. 0 volts.
11
VSSD
-
Ground for the digital part. 0 volts.
12
RLOS
O
Receive Loss-of-Signal.
This pin is set high on loss of the incoming signal at RIN.
13
EXCLK
I
External Reference Clock.
A valid DS3 or STS-1 clock must be provided at this input.
The duty cycle of
EXCLK, referenced to VDD/2 levels, must be 40% - 60%.
The EXCLK
frequency determines the operating frequency of the device.
14
VDDD
-
Power Supply for the digital part. +3.3 volts
15
VDDA
-
Power Supply for the analog part. +3.3 volts.
16
VDDC
-
Power Supply for the output buffer. +3.3 volts.
17
RCLK
O
Recovered Clock.
18
RNDATA
O
Receive Negative Data.
19
RPDATA
O
Receive Positive Data.
20
VSSC
-
Ground for the output buffer. 0 volts.
21
VSSA
-
22
VSSA
-
Ground for the analog part. 0 volts.
23
MODE1
I
24
MODE2
I
Mode Control.
Equalizer enable/bypass mode, Test mode are selectable as shown in
Table 4.
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