參數(shù)資料
型號: AK4367
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: OUTPUT MIXER & HP - AMP 24 BIT 2 CH DAC
中文描述: 輸出混音器
文件頁數(shù): 5/38頁
文件大?。?/td> 433K
代理商: AK4367
ASAHI KASEI
[AK4367]
MS0247-E-01
2004/11
- 13 -
OPERATION OVERVIEW
System Clock
The external clocks required to operate the AK4367 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master
clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter.
The frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency.
Table 1 shows system clock example.
LRCK
MCLK (MHz)
BICK (MHz)
fs
256fs
384fs
512fs
64fs
8kHz
2.048
3.072
4.096
0.512
11.025kHz
2.8224
4.2336
5.6448
0.7056
12kHz
3.072
4.608
6.144
0.768
16kHz
4.096
6.144
8.192
1.024
22.05kHz
5.6448
8.4672
11.2896
1.4112
24kHz
6.144
9.216
12.288
1.536
32kHz
8.192
12.288
16.384
2.048
44.1kHz
11.2896
16.9344
22.5792
2.8224
48kHz
12.288
18.432
24.576
3.072
Table 1. System Clock Example
All external clocks (MCLK, BICK and LRCK) should always be present whenever the DAC is in normal operation mode
(PMDAC bit = “1”). If these clocks are not provided, the AK4367 may draw excess current and will not operate properly
because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the DAC
should be placed in power-down mode (PMDAC bit = “0”). When MCLK is input with AC coupling, the MCKAC bit
should be set to “1”.
For low sampling rates, DR and S/N degrade because of the outband noise. DR and S/N are improved by setting DFS1 bit
to “1”. Table 2 shows S/N of DAC output for both the HP-amp and MOUT. When the DFS1 bit is “1”, MCLK needs
512fs.
S/N (fs=8kHz, A-weighted)
DFS1
DFS0
Over Sample
Rate
fs
MCLK
HP-amp
MOUT
0
64fs
8kHz
48kHz
256fs/384fs/512fs
56dB
Default
0
1
128fs
8kHz
24kHz
256fs/384fs/512fs
75dB
1
x
256fs
8kHz
12kHz
512fs
92dB
90dB
Table 2. Relationship among fs, MCLK frequency and S/N of HP-amp and MOUT
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