參數(shù)資料
型號: AK4626
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: HIGH PERFORMANCE MULTI-CHANNEL AUDIO CODEC
中文描述: 高性能多通道音頻解碼器
文件頁數(shù): 3/40頁
文件大小: 570K
代理商: AK4626
ASAHI KASEI
[AK4626]
MS0233- J -01
2004/03
- 11 -
(Ta=25
; AVDD, DVDD=4.5
5.5V; TVDD=2.75.5V; C
L=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
256fsn, 128fsd:
Pulse Width Low
Pulse Width High
384fsn, 192fsd:
Pulse Width Low
Pulse Width High
512fsn, 256fsd:
Pulse Width Low
Pulse Width High
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
8.192
27
12.288
20
16.384
15
12.288
18.432
24.576
MHz
ns
MHz
ns
MHz
ns
LRCK Timing
Normal mode (TDM0= “0”, TDM1= “0”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
32
64
120
45
48
96
192
55
kHz
%
TDM256 mode (TDM0= “1”, TDM1= “0”)
LRCK frequency
“H” time
“L” time
fsn
tLRH
tLRL
32
1/256fs
48
kHz
ns
TDM128 mode (TDM0= “1”, TDM1= “1”)
LRCK frequency
“H” time
“L” time
fsd
tLRH
tLRL
64
1/128fs
96
kHz
ns
Audio Interface Timing
Normal mode (TDM0= “0”, TDM1= “0”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “
↑”
(Note 18)
BICK “
↑” to LRCK Edge
(Note 18)
LRCK to SDTO(MSB)
BICK “
↓” to SDTO
SDTI1-3,DAUX Hold Time
SDTI1-3,DAUX Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
81
32
20
40
ns
TDM256 mode (TDM0= “1”, TDM1= “0”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “
↑”
(Note 18)
BICK “
↑” to LRCK Edge
(Note 18)
BICK “
↓” to SDTO
SDTI1 Hold Time
SDTI1 Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
20
10
20
ns
TDM128 mode (TDM0= “1”, TDM1= “1”)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “
↑”
(Note 18)
BICK “
↑” to LRCK Edge
(Note 18)
BICK “
↓” to SDTO
SDTI1-2 Hold Time
SDTI1-2 Setup Time
tBCK
tBCKL
tBCKH
tLRB
tBLR
tBSD
tSDH
tSDS
81
32
20
10
20
ns
Notes: 18.
LRCK
BICK
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