ASAHI KASEI
[AK4641]
MS0301-E-00
2004/05
- 44 -
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
0AH
ALC Mode Control 2
0
REF6
REF5
REF4
REF3
REF2
REF1
REF0
R/W
RD
R/W
Default
0
1
0
1
0
REF6-0: Set the Reference value at ALC1 Recovery Operation
During the ALC1 recovery operation, if the IPGA value exceeds the setting reference value by gain operation, then
the IPGA does not become larger than the reference value. For example, when REF6-0 bits = “30H”, RATT =
2step, IPGA = “2FH”, even if the input signal does not exceed the “ALC1 Recovery Waiting Counter Reset Level”,
the IPGA does not change to “2FH” + 2step = “31H”, but keeps “30H”. Default is “36H”.
REF6-0
GAIN (dB)
STEP
47H
+27.5
46H
+27.0
45H
+26.5
:
36H
+19.0
Default
:
10H
+0.0
:
06H
5.0
05H
5.5
04H
6.0
03H
6.5
02H
7.0
01H
7.5
00H
8.0
0.5dB
Table 23. Setting Reference Value at ALC1 Recovery Operation
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
0BH
Input PGA Control
0
IPGA6
IPGA5
IPGA4
IPGA3
IPGA2
IPGA1
IPGA0
R/W
RD
R/W
Default
0
1
0
IPGA6-0: Input Analog PGA (See Table 7.)
When IPGA gain is changed, IPGA6-0 bits should be written while PMMIC bit is “1” and ALC1 bit is “0”. IPGA
gain is reset when PMMIC bit is “0”, and then IPGA operation starts from the default value when PMMIC is
changed to “1”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by ALC1 operation.
When IPGA6-0 bits are read, the register values written by the last write operation is read out regardless the actual
gain.
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
0CH
Lch Digital ATT Control
ATTL7
ATTL6
ATTL5
ATTL4
ATTL3
ATTL2
ATTL1
ATTL0
0DH
Rch Digital ATT Control
ATTR7
ATTR6
ATTR5
ATTR4
ATTR3
ATTR2
ATTR1
ATTR0
R/W
Default
0
ATTL/R7-0: Digital ATT Output Control
These bits control the attenuation level of DAC output of Stereo CODEC. Step size of ATT is approximately
0.5dB (See Table 13).
Note) Even if DATTC bit = “1”, ATTR7-0 bits are not changed when the ATTL7-0 bits are written.