參數(shù)資料
型號: ALD1726GSAL
廠商: Advanced Linear Devices Inc
文件頁數(shù): 4/9頁
文件大?。?/td> 0K
描述: IC OPAMP GP R-R CMOS 8SOIC
標(biāo)準(zhǔn)包裝: 50
放大器類型: 通用
電路數(shù): 1
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 0.17 V/µs
增益帶寬積: 400kHz
電流 - 輸入偏壓: 0.01pA
電壓 - 輸入偏移: 150µV
電流 - 電源: 25µA
電流 - 輸出 / 通道: 200µA
電壓 - 電源,單路/雙路(±): 2 V ~ 10 V,±1 V ~ 5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
其它名稱: 1014-1098
ALD1726/ALD1726G
Advanced Linear Devices
4 of 9
Design & Operating Notes:
1. The ALD1726/ALD1726G CMOS operational amplifier uses a 3 gain
stage architecture and an improved frequency compensation scheme
to achieve large voltage gain, high output driving capability, and better
frequency stability. In a conventional CMOS operational amplifier
design, compensation is achieved with a pole splitting capacitor
together with a nulling resistor. This method is, however, very bias
dependent and thus cannot accommodate the large range of supply
voltage operation as is required from a stand alone CMOS operational
amplifier. The ALD1726/ALD1726G is internally compensated for
unity gain stability using a novel scheme that does not use a nulling
resistor. This scheme produces a clean single pole roll off in the gain
characteristics while providing for more than 70 degrees of phase
margin at the unity gain frequency.
2. The ALD1726/ALD1726G has complementary p-channel and n-
channel input differential stages connected in parallel to accomplish
rail to rail input common mode voltage range. This means that with the
ranges of common mode input voltage close to the power supplies,
one of the two differential stages is switched off internally. To maintain
compatibility with other operational amplifiers, this switching point has
been selected to be about 1.5V below the positive supply voltage.
Since offset voltage trimming on the ALD1726/ALD1726G is made
when the input voltage is symmetrical to the supply voltages, this
internal switching does not affect a large variety of applications such
as an inverting amplifier or non-inverting amplifier with a gain larger
than 2.5 (5V operation), where the common mode voltage does not
make excursions below this switching point.
The user should,
however, be aware that this switching does take place if the opera-
tional amplifier is connected as a unity gain buffer and should make
provision in his design to allow for input offset voltage variations.
3. The input bias and offset currents are essentially input protection
diode reverse bias leakage currents, and are typically less than 1pA
at room temperature. This low input bias current assures that the
analog signal from the source will not be distorted by input bias
currents. Normally, this extremely high input impedance of greater
than 1012
would not be a problem as the source impedance would
limit the node impedance. However, for applications where source
impedance is very high, it may be necessary to limit noise and hum
pickup through proper shielding.
4. The output stage consists of class AB complementary output drivers,
capable of driving a low resistance load. The output voltage swing is
limited by the drain to source on-resistance of the output transistors
as determined by the bias circuitry, and the value of the load resistor.
When connected in the voltage follower configuration, the oscillation
resistant feature, combined with the rail to rail input and output feature,
makes an effective analog signal buffer for medium to high source
impedance sensors, transducers, and other circuit networks.
5. ALD1726/ALD1726G operational amplifier has been designed to
provide full static discharge protection. Internally, the design has been
carefully implemented to minimize latch up. However, care must be
exercised when handling the device to avoid strong static fields that
may degrade a diode junction, causing increased input leakage
currents. In using the operational amplifier, the user is advised to
power up the circuit before, or simultaneously with, any input voltages
applied and to limit input voltages to not exceed 0.3V of the power
supply voltage levels.
6. The ALD1726/ALD1726G, with its micropower operation, offers
numerous benefits in reduced power supply requirements, less
noise coupling and current spikes, less thermally induced drift, better
overall reliability due to lower self heating, and lower input bias
current. It requires practically no warm up time as the chip junction
heats up to 0.1
°C or less above ambient temperature under most
operating conditions.
7. The ALD1726/ALD1726G has an internal design architecture that
provides robust high temperature operation. Contact factory for
custom screening versions.
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP VOLTAGE GAIN AS AFUNCTION
OF LOAD RESISTANCE
10M
LOAD RESISTANCE (
)
10K
100K
1M
1000
100
10
1
OPEN
LOOP
VOLTAGE
GAIN
(V/mV)
VS = ±2.5V
TA = 25°C
COMMON MODE INPUT VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
COMMON
MODE
INPUT
VOLTAGE
RANGE
(V)
±7
±6
±5
±4
±3
±2
±1
0
±1
±2
±3
±4
±5
±6
±7
TA = 25°C
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
100
80
40
60
0
20
SUPPLY
CURRENT
(
A)
0
±1
±2
±3
±4
±5
±6
TA = -55°C
+25
°C
+70
°C
+125
°C
INPUTS GROUNDED
OUTPUT UNLOADED
-25
°C
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (
°C)
100
10
1.0
0.01
0.1
INPUT
BIAS
CURRENT
(pA)
100
-25
0
75
125
50
25
-50
1000
VS = ±2.5V
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