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參數(shù)資料
| 型號(hào)： | AM1808BZWT4 |
| 廠商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 242/264頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM9 MPU 361NFBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | ARM9 |
| 處理器類(lèi)型： | ARM 微處理器 |
| 速度： | 456MHz |
| 電壓： | 1.25 V ~ 1.35 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 361-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 361-NFBGA（16x16） |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | 296-28241 |
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2000 N
Max PLL Lock Time =
m
where N = Pre-Divider Ratio
M = PLL Multiplier
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
Table 6-4. Allowed PLL Operating Conditions (PLL0 and PLL1)
NO
Default
PARAMETER
MIN
MAX
UNIT
.
Value
1
PLLRST: Assertion time during initialization
N/A
1000
N/A
ns
Lock time: The time that the application has to wait for
OSCIN
2
the PLL to acquire lock before setting PLLEN, after
N/A
cycles
changing PREDIV, PLLM, or OSCIN
3
PREDIV: Pre-divider value
/1
/32
30 (if internal oscillator is used)
4
PLLREF: PLL input frequency
12
MHz
50 (if external clock source is used)
5
PLLM: PLL multiplier values(1)
x20
x4
x32
6
PLLOUT: PLL output frequency
N/A
300
600
MHz
7
POSTDIV: Post-divider value
/1
/32
(1)
The multiplier values must be chosen such that the PLL output frequency (at PLLOUT) is between 300 and 600 MHz, but the frequency
going into the SYSCLK dividers (after the post divider) cannot exceed the maximum clock frequency defined for the device at a given
voltage operating point.
6.6.2
Device Clock Generation
PLL0 is controlled by PLL Controller 0 and PLL1 is controlled by PLL Controller 1. PLLC0 and PLLC1
manage the clock ratios, alignment, and gating for the system clocks to the chip. The PLLCs are
responsible for controlling all modes of the PLL through software, in terms of pre-division of the clock
inputs (PLLC0 only), multiply factors within the PLLs, and post-division for each of the chip-level clocks
from the PLLs outputs. PLLC0 also controls reset propagation through the chip, clock alignment, and test
points.
PLLC0 provides clocks for the majority of the system but PLLC1 provides clocks to the mDDR/DDR2
Controller and the ASYNC3 clock domain to provide frequency scaling immunity to a defined set or
peripherals. The ASYNC3 clock domain can either derive its clock from PLL1_SYSCLK2 (for frequency
scaling immunity from PLL0) or from PLL0_SYSCLK2 (for synchronous timing with PLL0) depending on
the application requirements. In addition, some peripherals have specific clock options independent of the
ASYNC clock domain.
6.6.3
Dynamic Voltage and Frequency Scaling (DVFS)
The processor supports multiple operating points by scaling voltage and frequency to minimize power
consumption for a given level of processor performance.
Frequency scaling is achieved by modifying the setting of the PLL controllers’ multipliers, post-dividers
(POSTDIV), and system clock dividers (SYSCLKn). Modification of the POSTDIV and SYSCLK values
does not require relocking the PLL and provides lower latency to switch between operating points, but at
the expense of the frequencies being limited by the integer divide values (only the divide values are
altered the PLL multiplier is left unmodified). Non integer divide frequency values can be achieved by
changing both the multiplier and the divide values, but when the PLL multiplier is changed the PLL must
relock, incurring additional latency to change between operating points. Detailed information on modifying
the PLL Controller settings can be found in SPRUGM9 - AM1808/AM1810 ARM Microprocessor System
Reference Guide.
Voltage scaling is enabled from outside the device by controlling an external voltage regulator. The
processor may communicate with the regulator using GPIOs, I2C or some other interface. When switching
between voltage-frequency operating points, the voltage must always support the desired frequency.
When moving from a high-performance operating point to a lower performance operating point, the
frequency should be lowered first followed by the voltage. When moving from a low-performance operating
point to a higher performance operating point, the voltage should be raised first followed by the frequency.
Voltage operating points refer to the CVdd voltage at that point. Other static supplies must be maintained
at their nominal voltages at all operating points.
Copyright 2010–2014, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
79
Product Folder Links: AM1808
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參數(shù)描述 |
|---|---|
| AM1808BZWTA3 | 功能描述:微處理器 - MPU ARM MicroProc RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| AM1808BZWTA4 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:AM1808 ARM Microprocessor |
| AM1808BZWTD3 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:AM1808 ARM Microprocessor |
| AM1808BZWTD4 | 功能描述:微處理器 - MPU ARM MicroProc RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類(lèi)型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| AM1808BZWTT3 | 制造商:Texas Instruments 功能描述:IC ARM9 CORTEX MPU 361NFBGA 制造商:Texas Instruments 功能描述:AM1808BZWTT3 |
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