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參數(shù)資料
| 型號： | AM24LC16SA |
| 英文描述： | 2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM |
| 中文描述： | 2線串行16K的位（2048 × 8）的CMOS電可擦除可編程ROM |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 203K |
| 代理商： | AM24LC16SA |
2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM
AM24LC16
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
2/10
ATC
Functional Description (Continued)
Devices Addressing
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit
device code (1010) for the AM24LC16, 3-bit page
address (A2 A1 A0) and 1-bit value indicating the
read or write mode. All I2C EEPROMs use and
internal protocol that defines a PAGE BLOCK size of
16K bits. The eighth bit of slave address determines
if the master device wants to read or write to the
AM24LC16. (Refer to table B).
The
AM24LC16
monitors
the
bus
for
its
corresponding slave address all the time. It
generates an acknowledge bit if the slave address
was true and it is not in a programming mode.
Table B
Operation
Control Code
Chip
Select
R/W
Read
Write
1010
A2 A1 A0
1
0
A0, A1, A2 is no connect
Write Operations
Byte Write
Following the start signal from the master, the slave
address is placed onto the bus by the master
transmitter. This indicates to the addressed slave
receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle.
Therefore the next byte transmitted by the master is
the word address and will be written into the address
pointer of the AM24LC16. After receiving another
acknowledge signal from the AM24LC16 the master
device will transmit the data word to be written into
the addressed memory location. The AM24LC16
acknowledges again and the master generates a
stop condition. This initiates the internal write cycle,
and during this period the AM24LC16 will not
generate acknowledge signals. (Shown in Figure 4)
Page Write
The write control byte, word address and the first
data byte are transmitted to the AM24LC16 in the
same way as in a byte write. But instead of
generating a stop condition the master transmit up
to 16 data bytes to the AM24LC16 which are
temporarily stored in the on-chip page buffer and will
be written into the memory after the master has
transmitted a stop condition. If the master transmits
more than 16 bytes prior to generating the stop
condition, the address counter will roll over and the
previously received data will be overwritten. As with
the byte write operation, once the stop condition is
received an internal write cycle will begin. (Shown in
Figure 5).
Acknowledge Polling
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle
is complete (this feature can be used to maximize
bus throughout). Once the stop condition for a write
command has been issued from the master, the
device initiates the internally timed write cycle. ACK
polling can be initiated immediately. This involves
the master sending a start condition followed by the
control byte for a write command (R/W = 0). If the
device is still busy with the write cycle, then no ACK
will returned. If the cycle is complete then the device
will return the ACK and the master can then proceed
with the next read or write commands.
Write Protection
Programming will not take place if the WP pin of the
AM24LC16 is connected to Vcc. The AM24LC16 will
accept slave and byte addresses; but if the memory
accessed is write protected by the WP pin, the
AM24LC16 will not generate an acknowledge after
the first byte of data has been received, and thus the
programming cycle will not be started when the stop
condition is asserted.
Read Operations
Read operations are initiated in the same way as
write operations with the exception that the R/W bit
of the slave address is set to one. There are three
basic types of read operations: current address read,
random read, and sequential read.
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