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參數(shù)資料
| 型號： | AM24LC16V |
| 英文描述： | 2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM |
| 中文描述： | 2線串行16K的位（2048 × 8）的CMOS電可擦除可編程ROM |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 203K |
| 代理商： | AM24LC16V |
2-Wire Serial 16K-bits (2048 x 8) CMOS Electrically Erasable PROM
AM24LC16
Anachip Corp.
www.anachip.com.tw
Rev. A1 Oct 20, 2003
3/10
ATC
Electrical Characteristics
DC Electrical Characteristics (Vcc =2.7~5.5V, Ta = 25oC )
AM24LC16
Parameter
Symbol
Conditions
Min
Max
Units
Operating Current (Program) **
ICC1
SCL = 100KHZ CMOS Input Levels
—
3
mA
Operating Current (Read) **
ICC2
SCL = 100KHZ CMOS Input Levels
—
200
A
Standby Current
ISB1
SCL=SDA=0V, Vcc=5V
—
10
A
Standby Current
ISB2
SCL=SDA=0V, Vcc=3V
—
1
A
Input Leakage
IIL
VIN = 0 V to VCC
-1
+1
A
Output Leakage
IOL
VOUT = 0 V to Vcc
-1
+1
A
Input Low Voltage**
VIL
-0.1
Vcc x 0.3
V
Input High Voltage**
VIH
Vcc x 0.7 VCC+ 0.2
V
Output Low Voltage
VOL1
IOL = 2.1mA TTL
—
0.4
V
Output Low Voltage
VOL2
IOL = 10uA CMOS
—
0.2
V
VCC Lockout Voltage
VLK
Programming Command Can Be
Executed
Default
—
V
Note ** : ICC1, ICC2, VIL min and VIH max are for reference only and are not tested.
Switching Characteristics (Under Operating Conditions)
AC Electrical Characteristics (Vcc =2.7~5.5V)
AM24LC16
Parameter
Symbol
Min
Max
Units
Clock frequency
Fscl
0
100
kHz
Clock high time
Thigh
4000
—
ns
Clock low time
Tlow
4700
—
ns
SDA and SCL rise time**
Tr
—
1000
ns
SDA and SCL fall time**
Tf
—
300
ns
START condition hold time
Thd:Sta
4000
—
ns
START condition setup time
Tsu:Sta
4700
—
ns
Data input hold time
Thd:Dat
0
—
ns
Data input setup time
Tsu:Dat
250
—
ns
STOP condition setup time
Tsu:Sto
4000
—
ns
Output valid from clock
Taa
300
3500
ns
Bus free time **
Tbuf
4700
—
ns
Data out hold time
Tdh
300
—
ns
Write cycle time
Twr
—
10
ms
5V, 25C, Byte Mode
Endurance**
1M
—
write cycles
Note **: This parameter is characterized and is not 100% tested.
Capacitance TA= 25°C , f=250KHz
Parameter
Symbol
Max
Units
Output capacitance
COUT
5
pF
Input capacitance
CIN
5
pF
AC. Conditions of Test
Input Pulse Levels
Vcc x 0.1 to Vcc x 0.9
Input Rise and Fall times
10 ns
Input and Output Timming level
Vcc x 0.5
Output Load
1 TTL Gate and CL = 100pf
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