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參數(shù)資料
| 型號(hào)： | AM27C256-255JC |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 256 Kilobit (32,768 x 8-Bit) CMOS EPROM |
| 中文描述： | 256千比特（32,768 × 8位）的CMOS存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 90K |
| 代理商： | AM27C256-255JC |
AMD
2-37
Am27C256
FUNCTIONAL DESCRIPTION
Erasing the Am27C256
In order to clear all locations of their programmed con-
tents, it is necessary to expose the Am27C256 to an
ultraviolet light source. A dosage of 15 W sec/cm
2
is
required to completely erase an Am27C256. This dos-
age can be obtained by exposure to an ultraviolet amp—
wavelength of 2537 A
°
—with intensity of 12,000
μ
W/cm
2
for 15 to 20 minutes. The Am27C256 should be directly
under and about one inch from the source and all filters
should be removed from the UV light source prior
to erasure.
It is important to note that the Am27C256 and similar
devices will erase with light sources having wavelengths
shorter than 4000 A
°
. Although erasure times will be
much longer than with UV sources at 2537 A
°
, exposure
to fluorescent light and sunlight will eventually erase the
Am27C256 and exposure to them should be prevented
to realize maximum system reliability. If used in such an
environment, the package window should be covered
by an opaque label or substance.
Programming the Am27C256
Upon delivery or after each erasure the Am27C256 has
all 262,144 bits in the “ONE” or HIGH state. “ZEROs”
are loaded into the Am27C256 through the procedure
of programming.
The programming mode is entered when 12.75 V
±
0.25 V is applied to the V
PP
pin,
OE
is at V
IH
, and
CE
is
at V
IL
.
For programming, the data to be programmed is applied
8 bits in parallel to the data output pins.
The Flashrite algorithm reduces programming time by
using 100
μ
s programming pulses and by giving each
address only as many pulses as is necessary in order to
reliably program the data. After each pulse is applied to
a given address, the data in that address is verified. If
the data does not verify, additional pulses are given until
it verifies or the maximum is reached. This process is re-
peated while sequencing through each address of the
Am27C256. This part of the algorithm is done at
V
CC
= 6.25 V to assure that each EPROM bit is pro-
grammed to a sufficiently high threshold voltage. After
the final address is completed, the entire EPROM mem-
ory is verified at V
CC
= V
PP
= 5.25 V.
Please refer to Section 6 for programming flow chart
and characteristics.
Program Inhibit
Programming of multiple Am27C256 in parallel with dif-
ferent data is also easily accomplished. Except for
CE
,
all like inputs of the parallel Am27C256 may be com-
mon. A TTL low-level program pulse applied to an
Am27C256
CE
input with V
PP
= 12.75 V
±
0.25 V, and
OE
High will program that Am27C256. A high-level
CE
input inhibits the other Am27C256 devices from
being programmed.
Program Verify
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The
verify should be performed with
OE
at V
IL,
CE
at V
IH,
and
V
PP
between 12.5 V to 13.0 V.
Auto Select Mode
The auto select mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and type. This mode is intended for use by programming
equipment for the purpose of automatically matching
the device to be programmed with its corresponding
programming algorithm. This mode is functional in the
25
°
C
±
5
°
C ambient temperature range that is required
when programming the Am27C256.
To activate this mode, the programming equipment
must force 12.0 V
±
0.5 V on address like A9 of the
Am27C256. Two identifier bytes may then be se-
quenced from the device outputs by toggling address
line A0 from V
IL
to V
IH
. All other address lines must be
held at V
IL
during auto select mode.
Byte 0 (A
0
= V
IL
) represents the manufacturer code, and
byte 1 (A
0
= V
IH
), the device code. For the Am27C256,
these two identifier bytes are given in the Mode Select
Table. All identifiers for manufacturer and device codes
will possess odd parity, with the MSB (DQ7) defined as
the parity bit.
Read Mode
The Am27C256 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (
CE
) is the power control and
should be used for device selection. Output Enable (
OE
)
is the output control and should be used to gate data to
the output pins, independent of device selection. As-
suming that addresses are stable, address access time
(t
ACC
) is equal to the delay from
CE
to output (t
CE
). Data
is available at the outputs t
OE
after the falling edge of
OE
, assuming that
CE
has been LOW and addresses
have been stable for at least t
ACC
–t
OE
.
Standby Mode
The Am27C256 has a CMOS standby mode which re-
duces the maximum V
CC
current to 100
μ
A. It is placed in
CMOS-standby when
CE
is at V
CC
±
0.3 V. The
Am27C256 also has a TTL-standby mode which re-
duces the maximum V
CC
current to 1.0 mA. It is placed in
TTL-standby when
CE
is at V
IH
. When in standby mode,
the outputs are in a high-impedance state, independent
of the
OE
input.
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