參數(shù)資料
型號: AM28F512-150JE
廠商: ADVANCED MICRO DEVICES INC
元件分類: PROM
英文描述: 8-Bit Identity/Magnitude Comparators (P=Q) with Enable 20-SO 0 to 70
中文描述: 64K X 8 FLASH 12V PROM, 150 ns, PQCC32
封裝: PLASTIC, LCC-32
文件頁數(shù): 17/35頁
文件大?。?/td> 484K
代理商: AM28F512-150JE
Am28F512
17
Table 5.
Flashrite Programming Algorithm
Notes:
1. See AC and DC Characteristics for values of V
PP
parameters. The V
PP
power supply can be hard-wired to the device or
switchable. When V
PP
is switched, V
PPL
may be ground, no connect with a resistor tied to ground, or less than V
CC
+ 2.0 V
2. Program Verify is performed only after byte programming. A final read/compare may be performed (optional) after the register
is written with the read command.
Bus Operations
Command
Comments
Standby
Wait for V
PP
Ramp to V
PPH
(Note 1)
Initialize Pulse counter
Write
Program Setup
Data = 40h
Program
Valid Address/Data
Standby
Duration of Programming Operation (t
WHWH1
)
Write
Program-Verify (Note 2)
Data = C0h Stops Program Operation
Standby
Write Recovery Time before Read = 6 μs
Read
Read Byte to Verify Programming
Standby
Compare Data Output to Data Expected
Write
Reset
Data = FFh, resets the register for read operations.
Standby
Wait for V
PP
Ramp to V
PPL
(Note 1)
相關(guān)PDF資料
PDF描述
AM28F512-150JEB 8-Bit Identity/Magnitude Comparators (P=Q) with Enable 20-SO 0 to 70
AM28F512-150JI 8-Bit Identity/Magnitude Comparators (P=Q) with Enable 20-SO 0 to 70
AM28F512-200JE Dual D-type pos.-edge-triggered flip-flops with preset and clear 14-SOIC 0 to 70
AM28F512-200JEB Dual D-type pos.-edge-triggered flip-flops with preset and clear 14-SSOP 0 to 70
AM28F512-200JI Dual D-type pos.-edge-triggered flip-flops with preset and clear 14-SSOP 0 to 70
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