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參數(shù)資料
| 型號： | AM28F512-200PIB |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory |
| 中文描述： | 64K X 8 FLASH 12V PROM, 200 ns, PDIP32 |
| 封裝： | PLASTIC, DIP-32 |
| 文件頁數(shù)： | 27/35頁 |
| 文件大小： | 484K |
| 代理商： | AM28F512-200PIB |
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Am28F512
27
AC Characteristics—Write/Erase/Program Operations
Notes:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC
Characteristics for Read Only operations.
2. Maximum pulse widths not required because the on-chip program/erase stop timer will terminate the pulse widths internally
on the device.
3. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In
systems where Chip-Enable defines the Write Pulse Width (within a longer Write-Enable timing waveform) all setup, hold and
inactive Write-Enable times should be measured relative to the Chip-Enable waveform.
4. Not 100% tested.
Parameter Symbols
Parameter Description
Am28F512 Speed Options
Unit
JEDEC
Standard
-70
-90
-120
-150
-200
t
AVAV
t
WC
Write Cycle Time (Note 4)
Min
70
90
120
150
200
ns
t
AVWL
t
AS
Address Setup Time
Min
0
0
0
0
0
ns
t
WLAX
t
AH
Address Hold Time
Min
45
45
50
60
75
ns
t
DVWH
t
DS
Data Setup Time
Min
45
45
50
50
50
ns
t
WHDX
t
DH
Data Hold Time
Min
10
10
10
10
10
ns
t
WHGL
t
WR
Write Recovery Time before Read
Min
6
6
6
6
6
μs
t
GHWL
Read Recovery Time before Write
Min
0
0
0
0
0
μs
t
ELWL
t
CS
Chip Enable Setup Time
Min
0
0
0
0
0
ns
t
WHEH
t
CH
Chip Enable Hold Time
Min
0
0
0
0
0
ns
t
WLWH
t
WP
Write Pulse Width
Min
45
45
50
60
60
ns
t
WHWL
t
WPH
Write Pulse Width HIGH
Min
20
20
20
20
20
ns
t
WHWH1
Duration of Programming Operation
(Note 2)
Min
10
10
10
10
10
μs
t
WHWH2
Duration of Erase Operation (Note 2)
Min
9.5
9.5
9.5
9.5
9.5
ms
t
VPEL
V
PP
Setup Time to Chip Enable LOW
(Note 4)
Min
100
100
100
100
100
ns
t
VCS
V
CC
Setup Time to Chip Enable LOW
(Note 4)
Min
50
50
50
50
50
μs
t
VPPR
V
PP
Rise Time 90% V
PPH
(Note 4)
Min
500
500
500
500
500
ns
t
VPPF
V
PP
Fall Time 10% V
PPL
(Note 4)
Min
500
500
500
500
500
ns
t
LKO
V
CC
< V
LKO
to Reset (Note 4)
Min
100
100
100
100
100
ns
相關(guān)PDF資料 |
PDF描述 |
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| AM28F512-70EC | Dual D-type pos.-edge-triggered flip-flops with preset and clear 14-PDIP 0 to 70 |
| AM28F512-70ECB | 512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory |
| AM28F512-70EE | Dual D-type pos.-edge-triggered flip-flops with preset and clear 14-PDIP 0 to 70 |
| AM28F512-70EEB | Dual D-type pos.-edge-triggered flip-flops with preset and clear 14-SO 0 to 70 |
| AM28F512-70EI | Dual D-type pos.-edge-triggered flip-flops with preset and clear 14-SO 0 to 70 |
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