參數資料
型號: AM28F512-70EI
廠商: ADVANCED MICRO DEVICES INC
元件分類: PROM
英文描述: Dual D-type pos.-edge-triggered flip-flops with preset and clear 14-SO 0 to 70
中文描述: 64K X 8 FLASH 12V PROM, 70 ns, PDSO32
封裝: TSOP-32
文件頁數: 10/35頁
文件大?。?/td> 484K
代理商: AM28F512-70EI
10
Am28F512
ERASE, PROGRAM, AND READ MODE
When V
PP
is equal to 12.0 V ± 5%, the command reg-
ister is active. All functions are available. That is, the
device can program, erase, read array or autoselect
data, or be standby mode.
Write Operations
High voltage must be applied to the V
PP
pin in order to
activate the command register. Data written to the reg-
ister serves as input to the internal state machine. The
output of the state machine determines the operational
function of the device.
The command register does not occupy an addressable
memory location. The register is a latch that stores the
command, along with the address and data information
needed to execute the command. The register is written
by bringing WE# and CE# to V
IL
, while OE# is at V
IH
.
Addresses are latched on the falling edge of WE#, while
data is latched on the rising edge of the WE# pulse.
Standard microprocessor write timings are used.
The device requires the OE# pin to be V
IH
for write op-
erations. This condition eliminates the possibility for
bus contention during programming operations. In
order to write, OE# must be V
IH
, and CE# and WE#
must be V
IL
. If any pin is not in the correct state a write
command will not be executed.
Refer to AC Write Characteristics and the Erase/Pro-
gramming Waveforms for specific timing parameters.
Command Definitions
The contents of the command register default to 00h
(Read Mode) in the absence of high voltage applied to
the V
PP
pin. The device operates as a read only mem-
ory. High voltage on the V
PP
pin enables the command
register. Device operations are selected by writing spe-
cific data codes into the command register. Table 3 de-
fines these register commands.
Read Command
Memory contents can be accessed via the read com-
mand when V
PP
is high. To read from the device, write
00h into the command register. Standard microproces-
sor read cycles access data from the memory. The de-
vice will remain in the read mode until the command
register contents are altered.
The command register defaults to 00h (read mode)
upon V
PP
power-up. The 00h (Read Mode) register de-
fault helps ensure that inadvertent alteration of the
memory contents does not occur during the V
PP
power
transition. Refer to the AC Read Characteristics and
Waveforms for the specific timing parameters.
Table 3.
Am28F512 Command Definitions
Notes:
1. Bus operations are defined in Table 1.
2. RA = Address of the memory location to be read.
EA = Address of the memory location to be read during erase-verify.
PA = Address of the memory location to be programmed.
X = Don’t care. Addresses are latched on the falling edge of the WE
#
pulse.
3. RD = Data read from location RA during read operation.
EVD = Data read from location EA during erase-verify.
PD = Data to be programmed at location PA. Data latched on the rising edge of WE
#
.
PVD = Data read from location PA during program-verify. PA is latched on the Program command.
4. Refer to the appropriate section for algorithms and timing diagrams.
Command (Note 4)
First Bus Cycle
Second Bus Cycle
Operation
(Note 1)
Address
(Note 2)
Data
(Note 3)
Operation
(Note 1)
Address
(Note 2)
Data
(Note 3)
Read Memory
Write
X
00H/FFh
Read
RA
RD
Read Auto select
Write
X
80h or 90h
Read
00h/01h
01h/25h
Erase Set-up/Erase Write
Write
X
20h
Write
X
20h
Erase-Verify
Write
EA
A0h
Read
X
EVD
Program Set-up/ Program
Write
X
40h
Write
PA
PD
Program-Verify
Write
X
C0h
Read
X
PVD
Reset
Write
X
FFh
Write
X
FFh
相關PDF資料
PDF描述
AM28F512-70EIB Quad bistable latches 16-SOIC 0 to 70
AM28F512-70FC 512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory
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