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參數(shù)資料
| 型號(hào)： | AM28F512-70FIB |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Quad bistable latches 16-PDIP 0 to 70 |
| 中文描述： | 512千比特（64畝× 8位）的CMOS 12.0伏，整體擦除閃存 |
| 文件頁(yè)數(shù)： | 31/35頁(yè) |
| 文件大?。?/td> | 484K |
| 代理商： | AM28F512-70FIB |
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Am28F512
31
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. 25°C, 12 V V
PP
.
2. Maximum time specified is lower than worst case. Worst case is derived from the Flasherase/Flashrite pulse count
(Flasherase = 1000 max and Flashrite = 25 max). Typical worst case for program and erase is significantly less than the actual
device limit.
LATCHUP CHARACTERISTICS
PIN CAPACITANCE
Note:
Sampled, not 100% tested. Test conditions T
A
= 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Limits
Comments
Min
Typ
(Note 1)
Max
(Note 2)
Unit
Chip Erase Time
1
10
sec
Excludes 00H programming prior to erasure
Chip Programming Time
1
6
sec
Excludes system-level overhead
Write/Erase Cycles
10,000
Cycles
Parameter
Min
Max
Input Voltage with respect to V
SS
on all pins except I/O pins (Including A9 and V
PP
)
–1.0 V
13.5 V
Input Voltage with respect to V
SS
on all pins I/O pins
–1.0 V
V
CC
+ 1.0 V
Current
–100 mA
+100 mA
Includes all pins except V
CC
. Test conditions: V
CC
= 5.0 V, one pin at a time.
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
8
10
pF
C
OUT
Output Capacitance
V
OUT
= 0
8
12
pF
C
IN2
V
PP
Input Capacitance
V
PP
= 0
8
12
pF
Parameter
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150°C
10
Years
125°C
20
Years
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM28F512-70JC | 512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory |
| AM28F512-70JCB | 512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory |
| AM28F512-70JE | 512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory |
| AM28F512-70JEB | 512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory |
| AM28F512-70JI | 512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory |
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