參數(shù)資料
型號(hào)： AM28F512A-70FIB
廠商： Advanced Micro Devices, Inc.
英文描述： Quadruple 2-Input Positive-Nor Gates 14-TVSOP -40 to 85
中文描述： 512千比特（64畝× 8位）的CMOS 12.0伏，整體擦除閃存的嵌入式記憶算法
文件頁(yè)數(shù)： 25/34頁(yè)
文件大?。?/td> 463K
代理商： AM28F512A-70FIB
31
Am28F512A
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. 25
°C, 12 V V
PP.
2. Maximum time specified is lower than worst case. Worst case is derived from the Embedded Algorithm internal counter which
allows for a maximum 6000 pulses for both program and erase operations. Typical worst case for program and erase is
significantly less than the actual device limit.
3. Typical worst case = 84 s. DQ5 = “1” only after a byte takes longer than 96 ms to program.
LATCHUP CHARACTERISTICS
PIN CAPACITANCE
Note: Sampled, not 100% tested. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Limits
Comments
Min
Typ
Max
Unit
Chip Erase Time
1
10
sec
Excludes 00h programming prior to erasure
Chip Programming Time
1
7
sec
Excludes system-level overhead
Write/Erase Cycles
100,000
Cycles
Byte Programming Time
14
s
96
ms
Parameter
Min
Max
Input Voltage with respect to VSS on all pins except I/O pins (Including A9 and VPP)
–1.0 V
13.5 V
Input Voltage with respect to VSS on all pins I/O pins
–1.0 V
VCC + 1.0 V
Current
–100 mA
+100 mA
Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.
Parameter
Symbol
Parameter Description
Test Conditions
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
8
10
pF
COUT
Output Capacitance
VOUT = 0
8
12
pF
CIN2
VPP Input Capacitance
VPP = 0
8
12
pF
Parameter
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150
°C
10
Years
125
°C
20
Years
相關(guān)PDF資料
PDF描述
AM28F512A-70JC Quadruple 2-Input Positive-Nor Gates 14-TVSOP -40 to 85
AM28F512A-70JCB Quadruple 2-Input Positive-Nor Gates 14-SOIC -40 to 85
AM28F512A-70JE Quadruple 2-Input Positive-Nor Gates 14-SOIC -40 to 85
AM28F512A-70JEB Quadruple 2-Input Positive-Nor Gates 14-SOIC -40 to 85
AM28F512A-70JI Quadruple 2-Input Positive-Nor Gates 14-SO -40 to 85
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