參數(shù)資料
型號(hào)： AM28F512A-70JIB
廠商： Advanced Micro Devices, Inc.
英文描述： Quadruple 2-Input Positive-Nor Gates 14-SO -40 to 85
中文描述： 512千比特（64畝× 8位）的CMOS 12.0伏，整體擦除閃存的嵌入式記憶算法
文件頁(yè)數(shù)： 1/34頁(yè)
文件大小： 463K
代理商： AM28F512A-70JIB
FINAL
Publication# 18880
Rev: C Amendment/+2
Issue Date: April 1998
Am28F512A
512 Kilobit (64 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
s High performance
— 70 ns maximum access time
s CMOS low power consumption
— 30 mA maximum active current
— 100 A maximum standby current
— No data retention power consumption
s Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
s 100,000 write/erase cycles minimum
s Write and erase voltage 12.0 V
5%
s Latch-up protected to 100 mA from -1 V
to VCC +1 V
s Embedded Erase Electrical Bulk Chip-Erase
— Two seconds typical chip-erase including
pre-programming
s Embedded Program
— 4 s typical byte-program including time-out
— One second typical chip program
s Command register architecture for
microprocessor/microcontroller compatible
write interface
s On-chip address and data latches
s Advanced CMOS flash memory technology
— Low cost single transistor memory cell
s Embedded algorithms for completely
self-timed write/erase operations
GENERAL DESCRIPTION
The Am28F512A is a 512 Kbit Flash memory orga-
nized as 64 Kbytes of 8 bits each. AMD’s Flash memo-
ries offer the most cost-effective and reliable read/write
non- volatile random access memory. The Am28F512A
is packaged in 32-pin PDIP, PLCC, and TSOP versions.
It is designed to be reprogrammed and erased in-sys-
tem or in sta ndard EPROM programmers. Th e
Am28F512A is erased when shipped from the factory.
The standard Am28F512A offers access times as fast
as 70 ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the Am28F512A has separate chip enable (CE#)
and output enable (OE#) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F512A uses a command register to manage this
functionality, while maintaining a JEDEC Flash stan-
dard 32-pin pinout. The command register allows for
100% TTL level control inputs and fixed power supply
levels during erase and programming.
AMD’s Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The AMD cell is designed to optimize the erase and
programming mechanisms. In addition, the combina-
tion of advanced tunnel oxide processing and low inter-
nal elec tr ic fields fo r erase a nd programmi ng
operations produces reliable cycling. The Am28F512A
uses a 12.0 V
±5% V
PP high voltage input to perform
the erase and programming functions.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 milliamps on
address and data pins from –1 V to VCC +1 V.
Embedded Program
The Am28F512A is byte programmable using the Em-
bedded Programming algorithm. The Embedded Pro-
gramming algorithm does not require the system to
time-out or verify the data programmed. The typical
r o o m te m p e r a t ur e pr ogr a m m i ng tim e o f th e
Am28F512A is one second.
Embedded Erase
The entire chip is bulk erased using the Embedded
Erase algorithm. The Embedded Erase algorithm auto-
matically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
相關(guān)PDF資料
PDF描述
AM28F512A-70PC 512 Kilobit (64 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
AM28F512A-70PCB Quadruple 2-Input Positive-Nor Gates 14-TSSOP -40 to 85
AM28F512A-70PE Quadruple 2-Input Positive-Nor Gates 14-TSSOP -40 to 85
AM28F512A-70PEB Quadruple 2-Input Positive-Nor Gates 14-TSSOP -40 to 85
AM28F512A-70PI Quadruple 2-Input Positive-Nor Gates 14-TSSOP -40 to 85
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