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參數(shù)資料
| 型號： | AM29BDD160GB54DPBE |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 512K X 32 FLASH 2.7V PROM, 54 ns, PBGA80 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, BGA-80 |
| 文件頁數(shù)： | 77/80頁 |
| 文件大?。?/td> | 3476K |
| 代理商： | AM29BDD160GB54DPBE |
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Am29BDD160G
77
Figure 17. Asynchronous Command Write
Timing
Added t
WC and tWPH.
Figure 18. Synchronous Command Write/ Read
Timing
Added t
WC and tWPH.
Hardware Reset (RESET#)
Corrected t
READY max.
Figure 20. WP# Write Timing
Added t
WP.
Figure 23. Back-to-back Cycle Timings
Added t
WPH.
Figure 24. Data# Polling Timings (During
Embedded Algorithms)
Added t
WC.
Figure 29. Alternate CE# Controlled Write
Operation Timings
Added t
WP and tWPH
Erase and Programming Performance
Changed the sector erase time typical to 1.0.
Revision B+5 (May 6, 2003) Global
Converted data sheet from Advanced Information to
Preliminary.
Ordering Information
Removed some OPNs and markings.
Automatic Sleep Mode (ASM) and Standby Mode
DQ7: Data# Polling, DQ6: Toggle Bit I and DQ2:
Toggle Bit II
Added reference to Figure 27.
Absolute Maximum Ratings
Added ACC reference.
CMOS Compatible
Corrected Max values for the I
CC5, 7, and 8 Added
Note #5.
Figure 27. Synchronous Data Polling Timings/
Toggle Bit Timing
Added Figure.
Simultaneous Read/Write Operations Overview
and Restrictions
Added Sections and table.
Table 7. Burst Initial Access Delay, Table 8.
Configuration Register Definitions, Table 23.
Test Specifications, Asynchronous Read
Operations, and Burst Mode Read
Removed the 65D, 80C, and 90A speed options from
tables.
Revision C (May 19, 2003)
No revisions made, re post on web.
Revision C+1 (May 29, 2003)
Distinctive Characteristics
Changed the standby mode to 60 A.
Product Selector Guide
Changed the standard voltage range to 2.5-2.75 V
Output Disable Mode
Replace paragraph.
Synchronous (Burst) Read Operation
Removed reference to “continuous sequential” from
section.
Figure 3. Initial Burst Delay Control
Renumbered waveform to read two, three, four.
Toggle Bit I
Added sentence to second paragraph of section.
CMOS Compatible
Removed reference to continuous burst from table.
Burst Mode Read
Changed the t
IACC Max for the 65A speed option
to 67 ns.
Reworded first paragraph.
Renumbered Supply Current axis, removed 2.3 V
graph, and changed other graph to 2.5 V.
Figure 27. Synchronous Data Polling Timing/
Toggle Bit Timings
Deleted line under the pulse in OE#.
Revision C+2 (June 26, 2003)
Product Selector Guide
Added Note.
Synchronous (Burst) Read Operation,
ADV#Control In Linear Mode, and IND/WAIT#
Operation in Linear Mode
Removed feature.
Table. 7 Valid Configuration Register Bit
Definition for IND/WAIT#
Removed features.
Table 20. Sector Protection Command
Definitions (x32 mode)
Changed the address for OW A5-A0 to 011X10.
Table 22. Sector Protection Command
Definitions (x16 mode)
Changed the PWA sector to A0:A-1
Figure 11. Typical I
CC1 vs. Frequency
Changed 2.5 to 2.7 and made T= 40°C
Trademarks
Burst Mode Read
Changed t
BACC for 54D to 9 FBGA and 9.5 PQFP.
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| AM29BDD160GB54DPBI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
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| AM29BDD160GB64CKK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
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