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參數(shù)資料
| 型號(hào)： | AM29BDD160GB64CKF |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| 中文描述： | 512K X 32 FLASH 2.7V PROM, 64 ns, PQFP80 |
| 封裝： | LEAD FREE, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 43/80頁(yè) |
| 文件大?。?/td> | 3476K |
| 代理商： | AM29BDD160GB64CKF |
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46
Am29BDD160G
DYB = Dynamic Protection Bit
OW = Address (A5–A0) is (011X10). PPB = Persistent Pro-
tection Bit
PWA = Password Address. A0 selects between the low and
high 32-bit portions of the 64-bit Password
PWD = Password Data. Must be written over two cycles.
PL = Password Protection Mode Lock Address (A5–A0) is
(001X10)
RD(0) = Read Data DQ0 protection indicator bit. If pro-
tected, DQ0= 1, if unprotected, DQ0 = 0.
RD(1) = Read Data DQ1 protection indicator bit. If pro-
tected, DQ1 = 1, if unprotected, DQ1 = 0.
SA = Sector Address where security command applies.
Address bits A18:A11 uniquely select any sector.
SL = Persistent Protection Mode Lock Address (A5–A0)
is (010X10)
WP = PPB Address (A5–A0) is (111X10)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells in table denote read cycles. All other cycles
are write operations.
4. During unlock cycles, (lower address bits are 555 or
2AAh as shown in table) address bits higher than A11
(except where BA is required) and data bits higher than
DQ7 are don’t cares.
5. The reset command returns the device to reading the ar-
ray.
6. The fourth cycle programs the addressed locking bit. The
fifth and sixth cycles are used to validate whether the bit
has been fully programmed. If DQ0 (in the sixth cycle)
reads 0, the program command must be issued and vil-
ified again.
7. Data is latched on the rising edge of WE#.
8. The entire four bus-cycle sequence must be entered for
each portion of the password.
9. The fourth cycle erases all PPBs. The fifth and sixth cy-
cles are used to validate whether the bits have been fully
erased. If DQ0 (in the sixth cycle) reads 1, the erase
command must be issued and verified again.
10. Before issuing the erase command, all PPBs should be
programmed in order to prevent over-erasure of PPBs.
11. In the fourth cycle, 00h indicates PPB set; 01h indicates
PPB not set.
12. The status of additional PPBs and DYBs may be read (fol-
lowing the fourth cycle) without reissuing the entire
command sequence.
DYB Status (12)
4
555
AA
2AA
55
(BA)
555
58
SA
RD(0)
PPMLB Program
(5,6)
6
555
AA
2AA
55
555
60
PL
68
PL
48
PL
RD(0)
PPMLB Status (5)
6
555
AA
2AA
55
555
60
PL
RD(0)
SPMLB Program
(5, 6)
6
555
AA
2AA
55
555
60
SL
68
SL
48
SL
RD(0)
SPMLB Status (5)
6
555
AA
2AA
55
555
60
SL
RD(0)
Table 20. Sector Protection Command Definitions (x32 Mode) (Sheet 2 of 2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29BDD160GB64CKI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB64CKK | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB65APBE | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GB65APBI | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
| AM29BDD160GT54DKE | 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory |
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