參數(shù)資料
型號(hào)： AM29BDD160GT65APBI
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： PROM
英文描述： 16 Megabit (1 M x 16-bit/512 K x 32-Bit), CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/Write Flash Memory
中文描述： 512K X 32 FLASH 2.7V PROM, 67 ns, PBGA80
封裝： 13 X 11 MM, 1 MM PITCH, BGA-80
文件頁(yè)數(shù)： 30/80頁(yè)
文件大?。?/td> 3476K
代理商： AM29BDD160GT65APBI
34
Am29BDD160G
During the data phase, the first burst data is avail-
able after the initial access time delay defined in the
Configuration Register. For subsequent burst data,
every rising (or falling) edge of the CLK will trigger
the output data with the burst output delay and se-
quence defined in the Configuration Register.
Tables 17–20 show all the commands executed by
the device. The device automatically powers up in
the read/reset state. It is not necessary to issue a
read/re-set command after power-up or hardware
reset.
Read/Reset Command
After power-up or hardware reset, the Am29BDD160
automatically enter the read state. It is not neces-
sary to issue the reset command after power-up or
hardware reset. Standard microprocessor cycles re-
trieve array data, however, after power-up, only
asynchronous accesses are permitted since the Con-
figuration Register is at its reset state with burst
accesses disabled.
The Reset command is executed when the user
needs to exit any of the other user command se-
quences (such as autoselect, program, chip erase,
etc.) to return to reading array data. There is no la-
tency between executing the Reset command and
reading array data.
The Reset command does not disable the SecSi sec-
tor if it is enabled. This function is only accomplished
by issuing the SecSi Sector Exit command.
Autoselect Command
Flash memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer and device codes must be acces-
sible while the device resides in the target system.
PROM programmers typically access the signature
codes by raising A9 to V
ID. However, multiplexing
high voltage onto the address lines is not generally
desired system design practice.
The Am29BDD160 contains an Autoselect Command
operation to supplement traditional PROM program-
ming methodology. The operation is initiated by
writing the Autoselect command sequence into the
command register. The bank address (BA) is latched
during the autoselect command sequence write op-
eration to distinguish which bank the Autoselect
command references. Reading the other bank after
the Autoselect command is written results in reading
array data from the other bank and the specified ad-
dress. Following the command write, a read cycle
from address (BA)XX00h retrieves the manufacturer
code of (BA)XX01h. Three sequential read cycles at
addresses (BA) XX01h, (BA) XX0Eh, and (BA) XX0Fh
read the three-byte device ID (see Tables 19 and
20). All manufacturer and device codes exhibit odd
parity with the MSB of the lower byte (DQ7) defined
as the parity bit.
(The Autoselect Command requires the user to exe-
cute the Read/Reset command to return the device
back to reading the array contents.)
Program Command Sequence
Programming is a four-bus-cycle operation. The pro-
gram command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are writ-
ten next, which in turn initiate the Embedded
Program algorithm. The system is not required to
provide further controls or timings. The device auto-
matically generates the program pulses and verifies
the programmed cell margin. Tables 18 and 20
shows the address and data requirements for the
program command sequence.
During the Embedded Program algorithm, the sys-
tem can determine the status of the program
operation by using DQ7, DQ6, or RY/BY#. (See Write
Operation Status for information on these status
bits.) When the Embedded Program algorithm is
complete, the device returns to reading array data
and addresses are no longer latched. Note that an
address change is required to begin read valid array
data.
Except for Program Suspend, any commands written
to the device during the Embedded Program Algo-
rithm are ignored. Note that a hardware reset
immediately terminates the programming operation.
The command sequence should be reinitiated once
that bank has returned to reading array data, to en-
sure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may
halt the operation and set DQ5 to “1,” or cause the
Data# Polling algorithm to indicate the operation
was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations
can convert a “0” to a “1”.
Accelerated Program Command
The Accelerated Chip Program mode is designed to
improve the Word or Double Word programming
speed. Improving the programming speed is accom-
plished by using the ACC pin to supply both the
word-line voltage and the bitline current instead of
using the V
PP pump and drain pump, which is limited
to 2.5 mA. Because the external ACC pin is capable
of supplying significantly large amounts of current
compared to the drain pump, all 32 bits are available
for programming with a single programming pulse.
This is an enormous improvement over the standard
5-bit programming. If the user is able to supply an
external power supply and connect it to the ACC pin,
significant time savings are realized.
In order to enter the Accelerated Program mode, the
ACC pin must first be taken to V
HH (12 V ± 0.5 V)
and followed by the one-cycle command with the
program address and data to follow. The Accelerated
Chip Program command is only executed
when the
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