參數(shù)資料
型號(hào)： AM29DL640H70WHIN
廠商： Advanced Micro Devices, Inc.
英文描述： 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
中文描述： 64兆位（8米× 8位/ 4米x 16位），3.0伏的CMOS只，同步讀/寫閃存
文件頁(yè)數(shù)： 30/54頁(yè)
文件大?。?/td> 880K
代理商： AM29DL640H70WHIN
28
Am29DL640H
February 9, 2005
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 13 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is com-
plete or in progress. The device also provides a hard-
ware-based output signal, RY/BY#, to determine whether
an Embedded Program or Erase operation is in progress or
has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether a bank is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the final
WE# pulse in the command sequence.
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 μs, then that bank returns to the
read mode.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 μs, then the
bank returns to the read mode. If not all selected sec-
tors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the
following
read cycles. Just prior to the completion of an
Embedded Program or Erase operation, DQ7 may
change asynchronously with DQ15–DQ8 (DQ7–DQ0
for x8-only device) while Output Enable (OE#) is as-
serted low. That is, the device may change from pro-
viding status information to valid data on DQ7.
Depending on when the system samples the DQ7 out-
put, it may read the status or valid data. Even if the de-
vice has completed the program or erase operation
and DQ7 has valid data, the data outputs on
DQ15–DQ0 may be still invalid. Valid data on
DQ15–DQ0 (or DQ7–DQ0 for x8-only device) will ap-
pear on successive read cycles.
Table 13 shows the outputs for Data# Polling on DQ7.
Figure 6 shows the Data# Polling algorithm. Figure 22
in the AC Characteristics section shows the Data#
Polling timing diagram.
Figure 6.
Data# Polling Algorithm
DQ7 = Data
Yes
No
No
DQ5 = 1
No
Yes
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
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