- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366405 > AM29DL642G90I (Advanced Micro Devices, Inc.) 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write Flash Memo PDF資料下載
參數(shù)資料
| 型號(hào)： | AM29DL642G90I |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write Flash Memo |
| 中文描述： | 128兆位（8米× 16位）的CMOS 3.0伏，只有同時(shí)讀/寫閃存?zhèn)渫?/td> |
| 文件頁數(shù)： | 12/54頁 |
| 文件大小： | 828K |
| 代理商： | AM29DL642G90I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
10
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
The device features an
Unlock Bypass
mode to facili-
tate faster programming. Once a bank enters the Un-
lock Bypass mode, only two write cycles are required
to program a word, instead of four. The “Word Pro-
gram Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies. Similarly, a “sector
address” is the address bits required to uniquely select
a sector. The “Command Definitions” section has de-
tails on erasing a sector or the entire chip, or suspend-
ing/resuming the erase operation.
The device address space is divided into four banks. A
“bank address” is the address bits required to uniquely
select a bank.
I
CC2
in the DC Characteristics table represents the ac-
tive current specification for the write mode. The
AC
Characteristics
section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
If the system asserts V
HH
on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
V
HH
from the WP#/ACC pin returns the device to nor-
mal operation.
Note that V
HH
must not be asserted on
WP#/ACC for operations other than accelerated pro-
gramming, or device damage may result. In addition,
the WP#/ACC pin must not be left floating or uncon-
nected; inconsistent behavior of the device may result
.
See “Write Protect (WP#)” on page 20. for related in-
formation.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Refer to the
Autoselect Mode
and
Autose-
lect Command Sequence
sections for more informa-
tion.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased). Figure 18 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. I
CC6
and I
CC7
in the
DC Characteristics
table
represent the current specifications for read-while-pro-
gram and read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# or CE2# and RESET# pins are both held at V
CC
±
0.3 V. (Note that this is a more restricted voltage range
than V
IH
.) If CE# and RESET# are held at V
IH
, but not
within V
CC
± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The de-
vice requires standard access time (t
CE
) for read ac-
cess when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the
DC Characteristics
table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+
30 ns. The automatic sleep mode is independent of
the CE#, CE2#, WE#, and OE# control signals. Stan-
dard address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
CC5
in the
DC Characteristics
table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29DL642G90MDI | 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Simultaneous Read/Write Flash Memo |
| AM29DL800BB120ED | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| AM29DL800BT120WBK | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| AM29DL800BT70ED | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| AM29DL800BT70EF | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29DL800BB-120WBD | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 8Mbit 1M/512K x 8bit/16bit 120ns 48-Pin FBGA |
| AM29DL800BB-70SI | 制造商:Spansion 功能描述:FLASH PARALLEL 3V/3.3V 8MBIT 1MX8/512KX16 70NS 44SOIC - Trays |
| AM29DL800BB-90EI | 制造商:Spansion 功能描述:NOR Flash Parallel 3V/3.3V 8Mbit 1M/512K x 8bit/16bit 90ns 48-Pin TSOP |
| AM29DL800BT-120EC | 制造商:Spansion 功能描述:SPZAM29DL800BT-120EC TB 120n EOL160610 |
| AM29DL800BT-120WBC | 制造商:Advanced Micro Devices 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。