參數(shù)資料
型號(hào)： AM29DL800BB120EC
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： PROM
英文描述： 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
中文描述： 1M X 8 FLASH 3V PROM, 120 ns, PDSO48
封裝： MO-142DD, TSOP-48
文件頁(yè)數(shù)： 8/43頁(yè)
文件大?。?/td> 580K
代理商： AM29DL800BB120EC
8
Am29DL800B
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is a latch used to store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29DL800B Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V, X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = V
IH
), A18:A-1 in byte mode (BYTE# = V
IL
).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE#
pin is set at logic ‘1’, the device is in word con-
figuration, DQ0-15 are active and controlled by CE#
and OE# .
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at V
IH
. The BYTE# pin determines whether the
device outputs array data in words or bytes.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs pro-
duce valid data on the device data outputs. EAch bank
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing spec-
ifications and to Figure 13 for the timing diagram. I
CC1
in the DC Characteristics table represents the active
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
Operation
CE#
L
L
V
CC
±
0.3 V
L
X
OE# WE# RESET#
L
H
H
L
Addresses
(Note 1)
A
IN
A
IN
DQ0–
DQ7
D
OUT
D
IN
DQ8–DQ15
BYTE#
= V
IH
D
OUT
D
IN
BYTE#
= V
IL
Read
Write
H
H
DQ8–DQ14 = High-Z,
DQ15 = A-1
Standby
X
X
V
CC
±
0.3 V
H
L
X
High-Z
High-Z
High-Z
Output Disable
Reset
H
X
H
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Sector Protect (Note 2)
L
H
L
V
ID
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Address,
A6 = H, A1 = H,
A0 = L
A
IN
D
IN
X
X
Sector Unprotect (Note 2)
L
H
L
V
ID
D
IN
X
X
Temporary Sector Unprotect
X
X
X
V
ID
D
IN
D
IN
High-Z
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Am29DL800BB120ECB 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
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