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參數(shù)資料
| 型號(hào)： | Am29DL800BB120EIB |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| 中文描述： | 8兆位（1 M中的x 8-Bit/512畝x 16位），3.0伏的CMOS只，同時(shí)作業(yè)快閃記憶體 |
| 文件頁數(shù)： | 15/43頁 |
| 文件大?。?/td> | 580K |
| 代理商： | AM29DL800BB120EIB |
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Am29DL800B
15
P R E L I M I N A R Y
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept
any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets to reading array data. Subsequent writes
are ignored until V
CC
is greater than V
LKO
. The system
must provide the proper signals to the control pins to
prevent unintentional writes when V
CC
is greater than
V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. Table 5 defines the valid register command
sequences. Writing
incorrect
address and data val-
ues
or writing them in the
improper sequence
resets
the device to reading array data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the AC
Characteristics section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-suspend-
read mode, after which the system can read data from
any non-erase-suspended sector within the same
bank. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See the Erase
Suspend/Erase Resume Commands section for more
information.
The system must issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation,
or if the bank is in the autoselect mode. See the next
section, Reset Command, for more information.
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read pa-
rameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the bank to which the sys-
tem was writing to reading array data. Once erasure
begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the bank to
which the system was writing to the reading array data.
If the program command sequence is written to a bank
that is in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read
mode. Once programming begins, however, the device
ignores reset commands until the operation is com-
plete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data. If a bank en-
tered the autoselect mode while in the Erase Suspend
mode, writing the reset command returns that bank to
the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to reading
array data (or erase-suspend-read mode if that bank
was in Erase Suspend).
相關(guān)PDF資料 |
PDF描述 |
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| AM29DL800BB120FC | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| Am29DL800BB120FCB | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| AM29DL800BB120FE | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| Am29DL800BB120FEB | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
| AM29DL800BB120FI | 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory |
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