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參數(shù)資料
| 型號(hào)： | Am29F002B-55JEB |
| 廠(chǎng)商： | Advanced Micro Devices, Inc. |
| 英文描述： | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 2兆位（256畝× 8位）的CMOS 5.0伏，只引導(dǎo)扇區(qū)閃存 |
| 文件頁(yè)數(shù)： | 7/37頁(yè) |
| 文件大?。?/td> | 436K |
| 代理商： | AM29F002B-55JEB |
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Am29F002/Am29F002N
7
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1.
Am29F002/Am29F002N Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V, X = Don’t Care, D
IN
= Data In, D
OUT
= Data Out, A
IN
= Address In
Note:
See the sections on Sector Protection and Temporary Sector Unprotect for more information. This function requires the
RESET# pin and is therefore not available on the Am29F002N device.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at V
IH
.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. I
CC1
in the DC Characteristics
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables in-
dicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the Command Defini-
tions section for details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and Autoselect
Command Sequence sections for more information.
I
CC2
in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
Operation
CE#
L
L
OE#
L
H
X
X
H
X
WE#
H
L
X
X
H
X
RESET#
(n/a Am29F002N)
H
H
H
H
H
L
A0–A17
A
IN
A
IN
X
X
X
X
DQ0–DQ7
D
OUT
D
IN
High-Z
High-Z
High-Z
High-Z
Read
Write
CMOS Standby
TTL Standby
Output Disable
Reset (n/a on Am29F002N)
Temporary Sector Unprotect
(See Note)
V
CC
± 0.5 V
H
L
X
X
X
X
V
ID
X
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM29F002BB-55ED | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| AM29F002BB-55EF | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| AM29F002BB-55JD | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| AM29F002BB-55JF | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| AM29F002BB-55PD | 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F002B-70JC | 制造商:Advanced Micro Devices 功能描述:NOR Flash, 256K x 8, 32 Pin, Plastic, PLCC |
| AM29F002BB-120EC | 制造商:Spansion 功能描述:2M (256KX8) 5V, BOOT BLOCK, BOT, TSOP32, COM - Trays |
| AM29F002BB-120JCT | 制造商:Spansion 功能描述:2M (256KX8) 5V, BOOT BLOCK, BOT, PLCC32, COM, T&R - Tape and Reel |
| AM29F002BB-55EC | 制造商:Spansion 功能描述: |
| AM29F002BB-55JF | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 2Mbit 256K x 8bit 55ns 32-Pin PLCC |
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